AT52SC1283J-70CI ATMEL [ATMEL Corporation], AT52SC1283J-70CI Datasheet
AT52SC1283J-70CI
Related parts for AT52SC1283J-70CI
AT52SC1283J-70CI Summary of contents
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... Page Read Cycle Time • 1.8V to 1.95V Operating Voltage • <10 µA Deep Standby Power Stack Module Memory Contents Device AT52SC1283J AT52SC1284J Memory Combination 128M Flash + 32M PSRAM 128M Flash + 64M PSRAM 128-Mbit Flash + 32-Mbit/64-Mbit PSRAM Stack Memory AT52SC1283J AT52SC1284J Preliminary 3530B–STKD–2/4/05 ...
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... Memory Module Description The AT52SC1283J/1284J memory module offers 128-megabit of nonvolatile Flash memory along with 32M/64M of PSRAM memory. The combined memory is packaged in a sin- gle 1.2 mm CBGA package with 88 balls. The Flash memory provides Asynchronous, Page and Burst Mode Read operation for the most optimum system performance ...
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... Respect to Ground ............................. -0. Voltage with Respect to Ground ..................................-0. 10.0V All Output Voltages with Respect to Ground ............................. -0. and AC Operating Range Operating Temperature (Case) V Power Supply CCQ VCC 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary] 3.1 88-ball CBGA Top View A18 C A5 PLB D A3 ...
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... A0 - A22 and captured by the AVD signal will be read when CE and OE are low. The address location passes into the device when CE and AVD are low; the address is latched on the low-to- high transition of AVD. Low input levels on the OE and CE pins allow the data to be driven out of AT52SC1283J/1284J [Preliminary] 4 page 21. The “ ...
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... D13 - D15, an output delay equal to the initial clock latency is incurred. The delay 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary] Word Boundary Word Word ...
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... Subsequent CLK edges resume the burst sequence where it left off. Within the device, OE gates the WAIT signal. Therefore, during Burst Suspend the WAIT signal reverts to a high-impedance state when OE is deasserted. page 34. AT52SC1283J/1284J [Preliminary] 6 page page 22. When operating in the linear burst read mode ( with the ...
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... Flexible Sector Protection The AT52SC1283J/1284J offers two sector protection modes, the Softlock and the Hardlock. The Softlock mode is optimized as sector protection for sectors whose content changes fre- quently. The Hardlock protection mode is recommended for sectors whose content changes infrequently ...
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... To disable the Hardlock sector protection mode, the chip must be either reset or power cycled. Table 6- AT52SC1283J/1284J [Preliminary] 8 Hardlock and Softlock Protection Configurations in Conjunction with WP Hard- Soft- WP lock lock ...
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... Read Status Register command is issued. The contents of the status register [SR7:SR0] are latched on the falling edge (whichever occurs last), which prevents possible bus errors that might occur if status register 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary] Sector Locking State Diagram UNLOCKED [000] ...
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... Figure 6-3. Read Status Register in the Burst Mode CLK CE OE AVD A22 XX I/O0 - I/O15 40H/10H (1) WAIT Note: 1. The WAIT signal is for a burst configuration setting of B10 and AT52SC1283J/1284J [Preliminary] 10 Table 6-3). A ADDRESS DATA 70H B 00H 80H 3530B–STKD–2/4/05 ...
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... A plane other than the one currently addressed is performing a program/erase operation. No program/erase operation is in progress in any plane. Erase and Program suspend bits (SR6, SR2 indicate whether other planes are suspended. 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary] ES PRS VPPS Check Write State Machine bit first to determine Word Program or Sector Erase completion, before checking program or erase status bits ...
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... Resume are valid commands during a Program Suspend. 6.16 Protection Registers The AT52SC1283J/1284J contains two (PR0 - PR1) registers that can be used for security pur- poses in system design. Please see address locations within each protection register. The first protection register (PR0) is divided into two 64-bit blocks. The two blocks are designated as block A and block B. The data in block A is non-changeable and is programmed at the factory with a unique number ...
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... Hardware Data Protection Hardware features protect against inadvertent programs to the AT52SC1283J/1284J in the fol- lowing ways: (a) V and erase functions are inhibited. (b) V level, the device will automatically time-out 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the inputs will not initiate a program cycle ...
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... Full Status Check Flowchart Read Status Register 1 SR3 = 0 1 SR4 = 0 1 SR1 = Protect Error 0 Program Successful AT52SC1283J/1284J [Preliminary] 14 6.22 Bus Operation Write Write Read Program Suspend Loop Idle No Yes Repeat for subsequent Word Program operations. Full status register check can be done after each program, or after a sequence of program operations ...
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... Data Done No Reading Yes Write D0 (Program Resume) Any Address Program Resumed Write 70H Any Address (Read Status) within the Same Plane 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary] 6.26 Operation Write Write Read Program Completed (Read Write FF Array) Write Read Data Read Write If the Suspend Plane was placed in Read mode: ...
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... Program? Program Read No Loop Done? Yes Write D0, (Erase Resume) Any Address Erase Resumed Write 70H Any Address (Read Status) within the Same Plane AT52SC1283J/1284J [Preliminary] 16 6.28 Bus Operation Write Write Read Erase Completed Idle Idle Write Read or (Read Array) Write FF Write Read Array ...
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... Sector SR5 = 0 1 Sector SR1 = 0 Sector Erase Successful 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary] 6.30 Operation Write Write Suspend Erase Loop Read No Yes Repeat for subsequent sector erasures. Full status register check can be done after each sector erase, or after a sequence of sector erasures. ...
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... SR1, SR4 = Program Error Register Locked; = SR1, SR4 Program Aborted 0 Program Successful AT52SC1283J/1284J [Preliminary] 18 6.34 Bus Operation Write Write Read Idle Program Protection Register operation addresses must be within the protection register address space. Addresses outside this space will return an error. Repeat for subsequent programming operations. ...
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... If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed. 11. D represents 16 bits of data. If all data bits are “0s”, the register is locked. OUT 12. See “Burst Configuration Register” on page 21. Addresses A16 - A22 can select any plane. 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary] 1st Bus Cycle Bus Cycles Addr Data (2) ...
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... User • • • PR1 A1 User 102 User • • • 109 User Note: 1. All address lines not specified in the above table must be 0 when accessing the Protection Register, i.e., A22 - AT52SC1283J/1284J [Preliminary ...
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... Figure 10-1. Output Configuration 1 CLK Data Hold ( CLK Data Hold ( 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary] Synchronous Burst Reads Enabled Asynchronous Reads Enabled Four-word Page Clock Latency of Two Clock Latency of Three Clock Latency of Four Clock Latency of Five Clock Latency of Six ...
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... AT52SC1283J/1284J [Preliminary] 22 Burst Addressing Sequence (Decimal) 4-word Burst Length 8-word Burst Length B2 – 001 B2 – 010 Linear Linear 0-1-2-3 0-1-2-3-4-5-6-7 1-2-3-0 1-2-3-4-5-6-7-0 2-3-0-1 2-3-4-5-6-7-0-1 3-0-1-2 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 • • • • • • ...
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... Memory Organization – AT52SC1283J/1284J Plane Size Plane (Bits • • 4M • • • 4M • • • 4M • • • 4M • • • 4M • 5 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary] Sector Size Words SA0 4K SA1 4K SA2 4K SA3 4K SA4 ...
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... Memory Organization – AT52SC1283J/1284J (Continued) Plane Size Plane (Bits) 6 • • 4M • • • 4M • • • 4M • • • 4M • • • 4M • • • 4M • • • 4M • • • 4M • 13 AT52SC1283J/1284J [Preliminary] ...
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... Memory Organization – AT52SC1283J/1284J (Continued) Plane Size Plane (Bits) 14 • • 4M • • • 4M • • • 4M • • • 4M • • • 4M • • • 4M • • • 4M • • • 4M • 21 3530B–STKD–2/4/05 ...
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... Memory Organization – AT52SC1283J/1284J (Continued) Plane Size Plane (Bits) 22 • • 4M • • • 4M • • • 4M • • • 4M • • • 4M • • • 4M • • • 4M • • • 4M • 29 AT52SC1283J/1284J [Preliminary] ...
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... Memory Organization – AT52SC1283J/1284J (Continued) Plane Size Plane (Bits) 30 • • 4M • • • • 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary] Sector Size Words SA247 32K • • • • • • SA254 32K SA255 32K SA256 32K • • ...
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... Reset X X Notes can Refer to AC programming waveforms. 3. Manufacturer Code: 001FH; Device Code: 00BBH 4. The VPP pin can be tied (min) = 0.9V. IHPP 6. V (max) = 0.4V. ILPP AT52SC1283J/1284J [Preliminary] 28 (4) WE RESET ( IHPP ...
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... Input Test Waveforms and Measurement Level 16. Output Test Load 17. Pin Capacitance ( MHz 25°C Typ OUT Note: 1. This parameter is characterized and is not 100% tested. 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary] Condition I 0. CCQ MHz OUT MHz ...
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... Asynchronous Read Cycle Waveform Notes may be delayed may be delayed without impact ACC specified from OE or CE, whichever occurs first ( pF AVD and CLK should be tied low. AT52SC1283J/1284J [Preliminary DATA VALID t ACC2 A2 -A22 t AAV t AHAV t ACC2 A0 -A1 ...
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... After the high-to-low transition on AVD, AVD may remain low as long as the page address is stable. 23. Page Read Cycle Waveform 2 CE I/O0-I/O15 A2 -A22 A0 -A1 (1) AVD OE RESET Note: 1. AVD may remain low as long as the page address is stable. 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary] ( DATA VALID t ACC2 t AAV t AHAV t PAA t ACC2 t AAV t AHAV t AVHP (1) ...
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... The WAIT signal (dashed line) shown is for a burst configuration register setting of B10 and The WAIT Signal (solid line) shown is for a burst configuration setting of B10 = 1 and After the high-to-low transition on AVD, AVD may remain low. AT52SC1283J/1284J [Preliminary CLK ...
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... CLK A0-A22 I/O0-I/O15 (1) WAIT Note: 1. Dashed line reflects a burst configuration register setting of B10 and Solid line reflects a burst configuration register setting of B10 = 1, B9 and 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary D13 D14 D15 D13 D14 D15 ...
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... WAIT Notes: 1. The WAIT signal (dashed line) shown is for a burst configuration register setting of B10 and The WAIT Signal (solid line) shown is for a burst configuration setting of B10 = 1 and During Burst Suspend, CLK signal can be held low or high. AT52SC1283J/1284J [Preliminary ...
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... CE Controlled WE I/O0-I/O15 A0 -A22 AVD CE Note: 1. After the high-to-low transition on AVD, AVD may remain low as long as the CLK input does not toggle. 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary] DATA VALID t AAV t AHAV AVLP t WP DATA VALID t AAV t AHAV AVLP ...
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... AC Word Load Waveforms 2 (1) 33.1 WE Controlled CE I/O0 - I/O15 A0 - A22 WE AVD Note: 1. The CLK input should not toggle. (1) 33.2 CE Controlled WE I/O0 - I/O15 A0 - A22 CE AVD Note: 1. The CLK input should not toggle. AT52SC1283J/1284J [Preliminary] 36 Min Max DATA VALID V IL DATA VALID V IL Units ...
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... For chip erase, any address can be used. For plane erase or sector erase, the address depends on what plane or sector erased. 5. For chip erase, the data should be 21H, for plane erase, the data should be 22H, and for sector erase, the data should be 20H. 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary] PROGRAM CYCLE ...
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... AT52SC1283J/1284J [Preliminary] 38 Comments 0051h “Q” 0052h “R” 0059h “Y” 0003h 0000h 0041h 0000h 0000h 0000h 0000h 0000h 0016h VCC min write/erase ...
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... AT52SC1283J/1284J [Preliminary] Comments VENDOR SPECIFIC EXTENDED QUERY 0050h “P” 0052h “R” 0049h “I” 0031h Major version number, ASCII 0030h Minor version number, ASCII 00BFh Bit 0 – ...
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... Very Low Standby Current – I SB0 • Very Low Operating Current – 1 µs (Typical) • Memory Expansion with PCS1 and POE • TTL Compatible Three-state Output Driver 40. Functional Block Diagram AT52SC1283J/1284J [Preliminary] 40 < < 10 µA Clk Gen Row Addresses I/O0 ~ I/O7 I/O8 ~ I/O15 PCS1 OE ...
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... Overshoot 1.0V in case of pulse width < Undershoot: -1.0V in case of pulse width < 20 ns. (1) 43. Capacitance ( MHz, T Item Symbol Input Capacitance C I/O Capacitance C Note: 1. Capacitance is sampled, not 100% tested. 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary] PLB PUB I/ I/ (1) ( High-Z High-Z (1) ( High-Z ...
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... Average Operating Current I CC2 Output Low Voltage V OL Output High Voltage V OH Standby Current (TTL Standby Current (CMOS) I SB1 Low Power Modes I SB0 AT52SC1283J/1284J [Preliminary] 42 Test Conditions V = PGND PCS1 = POE = PWE = PGND I/O CC Cycle time = 1 µ ...
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... Data Hold from Write Time End Write to Output Low-Z Page Mode Cycle Time Page Page Mode Address Access Time Maximum Cycle Time PCS1 High Pulse Width 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary] = 1.8V – 1.95V -25°C to 85° Speed Bins 70 ns Symbol ...
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... Maintain stable power for a minimum of 200 µs with PCS1 = V 47. Standby Mode State Machines Wait 200 µs PCS1 = Standby Mode 48. Standby Mode Characteristics Mode Standby Low Power Modes AT52SC1283J/1284J [Preliminary Power On PCS1 = V IH Initial State PCS1 = ...
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... HZ OHZ voltage levels any given temperature and voltage condition, t device interconnection not access device with cycle timing shorter than t 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary PWE = V , PUB or/and PLB = ...
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... PCS1 going low to end of write measured from the address valid to the beginning of write measured from the end of write to the address change not access device with cycle timing shorter than t AT52SC1283J/1284J [Preliminary ( (1) P ...
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... PCS1 going low to end of write measured from the address valid to the beginning of write measured from the end of write to the address change not access device with cycle timing shorter than t 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary] t MRC ...
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... Deep Power-down Mode Entry/Exit A4 PCS1 PUB, PLB PWE ZWE ZZ Parameter t ZZWE t (Deep Power-down Mode Only ZZmin AT52SC1283J/1284J [Preliminary (4) R ( ZZmin Register Deep Power Write (DPD) Down Start Description ZZ low to Write Enable Low Operation Recovery Time Low Power Mode Time ...
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... The register update takes place on the rising edge of ZZ. Once the register is updated, the next time ZZ goes low, without any updates to the register starting within the t care when ZZ is low during the register updates. 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary µs. ...
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... Ordering Information 53.1 AT52SC1283J Standard Package t ACC (ns) Ordering Code 85 AT52SC1283J-85CI 70 AT52SC1283J-70CI 53.2 AT52SC1284J Standard Package t ACC (ns) Ordering Code 85 AT52SC1284J-85CI 70 AT52SC1284J-70CI 88C1 88-ball, Plastic Chip-size Ball Grid Array Package (CBGA) AT52SC1283J/1284J [Preliminary] 50 Package 88C1 88C1 Package 88C1 88C1 Package Type Operation Range -25° to 85°C -25° ...
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... Bottom View 2325 Orchard Parkway San Jose, CA 95131 R 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary Ball Corner 0.60 mm Ref Øb TITLE 88C1, 88-ball ( Array 1.2 mm Body, 0.80 mm Ball Pitch Ball Grid Array Package (CBGA) ...
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 ...