AT52SC1283J-70CI ATMEL [ATMEL Corporation], AT52SC1283J-70CI Datasheet - Page 4

• Manufacturer Part Number: AT52SC1283J-70CI
• Description: 128-Mbit Flash + 32-Mbit/64-Mbit
• Manufacturer: ATMEL [ATMEL Corporation]

6. 128-Mbit Flash Description
6.1
6.2
6.3
4
Command Sequences
Burst Configuration Command
Asynchronous Read
AT52SC1283J/1284J [Preliminary]
When the device is first powered on, it will be in the read mode. Command sequences are used
to place the device in other operating modes such as program and erase. The command
sequences are written by applying a low pulse on the WE input with CE low and OE high or by
applying a low-going pulse on the CE input with WE low and OE high. Prior to the low-going
pulse on the CE or WE signal, the address input may be latched by a low-to-high transition on
the AVD signal. If the AVD is not pulsed low, the address will be latched on the first rising edge of
the WE or CE. Valid data is latched on the rising edge of the WE or the CE pulse, whichever
occurs first. The addresses used in the command sequences are not affected by entering the
command sequences.
The Program Burst Configuration Register command is used to program the burst configuration
register. The burst configuration register determines several parameters that control the read
operation of the device. Bit B15 determines whether synchronous burst reads are enabled or
asynchronous reads are enabled. Since the page read operation is an asynchronous operation,
bit B15 must be set for asynchronous reads to enable the page read feature. The rest of the bits
in the burst configuration register are used only for the burst read mode. Bits B13 - B11 of the
burst configuration register determine the clock latency for the burst mode. The latency can be
set to two, three, four, five or six cycles. The clock latency versus input clock frequency table is
shown on
of four; the data is output from the device four clock cycles after the first valid clock edge follow-
ing the high-to-low AVD edge. The B10 bit of the configuration register determines the polarity of
the WAIT signal. The B9 bit of the burst configuration register determines the number of clocks
that data will be held valid (see
is shown on
the burst configuration register determines when the WAIT signal will be asserted. When syn-
chronous burst reads are enabled, a linear burst sequence is selected by setting bit B7. Bit B6
selects whether the burst starts and the data output will be relative to the falling edge or the ris-
ing edge of the clock. Bits B2 - B0 of the burst configuration register determine whether a
continuous or fixed-length burst will be used and also determine whether a four-, eight- or six-
teen-word length will be used in the fixed-length mode. When a four-, eight- or sixteen-word
burst length is selected, Bit B3 can be used to select whether burst accesses wrap within the
burst length boundary or whether they cross word length boundaries to perform linear accesses
(See “Sequence and Burst Length Table” on page
register should be programmed as shown on
reset) of the burst configuration register is also shown on
There are two types of asynchronous reads – AVD pulsed and standard asynchronous reads.
The AVD pulsed read operation of the device is controlled by CE, OE, and AVD inputs. The out-
puts are put in the high-impedance state whenever CE or OE is high. This dual-line control
gives designers flexibility in preventing bus contention. The data at the address location defined
by A0 - A22 and captured by the AVD signal will be read when CE and OE are low. The address
location passes into the device when CE and AVD are low; the address is latched on the low-to-
high transition of AVD. Low input levels on the OE and CE pins allow the data to be driven out of
page
page
21. The “Burst Read Waveform” as shown on
33. The clock latency is not affected by the value of the B9 bit. The B8 bit of
Figure
10-1). The Hold Data for 2 Clock Cycles Read Waveform
page
22.). All other bits in the burst configuration
21. The default state (after power-up or
page
page 33
21.
illustrates a clock latency
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