AT52SC1283J-70CI ATMEL [ATMEL Corporation], AT52SC1283J-70CI Datasheet - Page 10

• Manufacturer Part Number: AT52SC1283J-70CI
• Description: 128-Mbit Flash + 32-Mbit/64-Mbit
• Manufacturer: ATMEL [ATMEL Corporation]

6.13.1
Figure 6-3.
Note:
10
I/O0 - I/O15
1. The WAIT signal is for a burst configuration setting of B10 and B8 = 0.
AT52SC1283J/1284J [Preliminary]
A0 - A22
Read Status Register In the Burst Mode
WAIT
AVD
CLK
WE
Read Status Register in the Burst Mode
CE
OE
(1)
contents change while being read. CE or OE must be toggled with each subsequent status read,
or the status register will not indicate completion of a Program or Erase operation.
When the Write State Machine (WSM) is active, SR7 will indicate the status of the WSM; the
remaining bits in the status register indicate whether the WSM was successful in performing the
preferred operation (see
The waveform below shows a status register read during a program operation. The two-bus
cycle command for a program operation is given followed by a read status register command.
Following the read status register command, the AVD signal is pulsed low to latch the valid
address at point A. With the OE signal pulsed low and for the specified clock latency of three, the
status register output is valid within 13 ns from clock edge B. The same status register data is
output on successive clock edges. To update the status register output, the AVD signal needs to
be pulsed low and the next data is available after a clock latency of three. The status register
output is also available after the chosen clock latency during an erase operation.
40H/10H
XX
ADDRESS
DATA
70H
Table
6-3).
A
B
00H
3530B–STKD–2/4/05
80H