UAA3522 PHILIPS [NXP Semiconductors], UAA3522 Datasheet - Page 7
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UAA3522
Manufacturer Part Number
UAA3522
Description
Low power dual-band GSM transceiver with an image rejecting front-end
Manufacturer
PHILIPS [NXP Semiconductors]
Datasheet
1.UAA3522.pdf
(28 pages)
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Philips Semiconductors
FUNCTIONAL DESCRIPTION
RF receiver
The receiver front-end converts the aerial RF signal, in the
GSM band (925 to 960 MHz), to an IF signal of
approximately 200 MHz. The first stage of the receiver is a
symmetrical LNA that is matched to 50
balun. The LNA is followed by an image rejection mixer
which suppresses the image by more than 30 dB.
It comprises two mixers in parallel driven by 0 and 90
quadrature LO signals respectively. The IF signal from
one mixer is shifted by 90 with respect to the IF signal
from the other mixer, then both signals are added together
to cancel out the image signal. The resultant IF signal is
fed to the output via a high output impedance
open-collector stage which drives an external Surface
Acoustical Wave (SAW) filter which selects the required
channel.
I/Q demodulator
The signal from the SAW filter enters the I/Q demodulator
section. In addition to I/Q demodulation, this section
performs Automatic Gain Control (AGC) over a range of
60 dB to maintain a constant output level irrespective of
the antenna input level, and also applies additional
channel selectivity at the baseband stage using an
integrated high-order low-pass filter.
The AGC amplifier output can be adjusted for a static
offset of less than 50 mV. Its design prevents the offset
from varying by more than 5 mV. To allow a more
accurate offset calibration, the RF LNA can be switched off
to ensure that no IF signal is present at the AGC amplifier
input during the offset measurement.
I/Q modulator
Baseband I and Q signals are applied to the I/Q modulator
which shifts the modulation spectrum up to the transmit IF.
The I/Q modulator is designed for low harmonic distortion,
low carrier leakage and high image rejection to keep the
phase error as small as possible. Its IF output is loaded by
an integrated low-pass filter and by an external
LC tuned-circuit to prevent unwanted spurii from entering
the phase detector in the transmit modulation loop.
Transmit modulation loop
The analog transmit modulation loop comprises an on-chip
offset mixer and simple phase detector in switching mode
(triangular transfer function) forming an analog PLL with
an off-chip loop filter and transmit RF VCO.
2000 Feb 18
Low power dual-band GSM transceiver
with an image rejecting front-end
by an external
7
The phase detector output transfers the modulation of the
I/Q IF signal to the off-chip transmit RF VCO making the
analog PLL act as a tracking filter. A PLL of at least
third-order is needed to meet noise requirements at
20 MHz offset from the carrier.
RF and IF LO sections
The active components required for the design of a low
noise IF VCO are provided on-chip. Pins IFLOC and
IFLOE connect the on-chip IF VCO components to an
external resonator and feedback circuit.
A divider and phase shifter divides the frequency of the
IF VCO signal by 2 and splits it into two signals having
phases of respectively 0 and 90 which are both fed to the
I/Q modulator and to the I/Q demodulator. The IF VCO
frequency is twice the IF to suppress the effects of
self-mixing and parasitic VCO modulation.
Pins TXIRFA and TXIRFAB connect an external receive
RF VCO module to the on-chip RF LO section. This
section includes a RC phase shifter which splits the
RF VCO signal into two signals having phases of
respectively 0 and 90 which are both fed to the RX
image rejection mixer.
Dual PLL
An on-chip high performance dual PLL synthesizes the
frequencies of the receive RF VCO and IF VCO signals.
Very low close-in phase noise is achieved which provides
a wide PLL bandwidth with a short settling time.
A dual programmable divider chain reduces the frequency
of the receive RF and IF LO signals to 200 kHz and 1 MHz
respectively. A digital phase/frequency detector compares
their phases to a reference signal derived from an external
13 MHz clock signal. Phase error information is fed back
to both VCOs via the dual charge pump circuit which
adjusts the phase of each VCO signal by either ‘sinking’
current into, or ‘sourcing’ current from, its loop filter
capacitor, phase locking both RF and IF loops. The very
low leakage current of the dual charge pump circuit
ensures that any spurii are negligible.
Operating modes
B
The circuit can be powered on in one of four operating
modes in which different parts of the device are enabled or
disabled. The four operating modes are called Idle, RX,
TX and SYN, and are selected by the hardware control
voltage level applied to pins RXON, TXON and SYNON.
ASIC OPERATING MODES
Objective specification
UAA3522HL