ZL50051 ZARLINK [Zarlink Semiconductor Inc], ZL50051 Datasheet - Page 47

• Manufacturer Part Number: ZL50051
• Description: 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

13.7
Address 014D
The Memory BIST Register enables the self-test of chip memory. Two consecutive write operations are required to
start MBIST: the first with only Bit 12 (LV_TM) set HIGH (i.e. 1000h); the second with Bit 12 maintained HIGH but
with the required start bit(s) also set HIGH.
The MBISTR register is configured as follows:
15:13
Bit
12
10
11
9
8
7
6
5
4
3
2
Memory BIST Register
Reserved
BISTSDB
BISTCDB
BISTPDB
BISTSCB
BISTCCB
BISTPCB
BISTSDL
BISTCDL
BISTPDL
BISTSCL
LV_TM
Name
H
.
Reset
Value
0
0
0
0
0
0
0
0
0
0
0
0
Table 23 - Memory BIST Register (MBISTR) Bits
Reserved
Must be set to 0 for normal operation
MBIST Test Enable
Set HIGH to enable MBIST mode.
Set LOW for normal operation.
Backplane Data Memory Start BIST Sequence
Sequence enabled on LOW to HIGH transition.
Backplane Data Memory BIST Sequence Completed (Read-only)
This bit must be polled - when HIGH, indicates completion of Backplane Data
Memory BIST sequence.
Backplane Data Memory Pass/Fail Bit (Read-only)
This bit indicates the Pass/Fail status following completion of the Backplane
Data Memory BIST sequence (indicated by assertion of BISTCDB).
A HIGH indicates Pass, a LOW indicates Fail.
Local Data Memory Start BIST Sequence
Sequence enabled on LOW to HIGH transition.
Local Data Memory BIST Sequence Completed (Read-only)
This bit must be polled - when HIGH, indicates completion of Local Data
Memory BIST sequence.
Local Data Memory Pass/Fail Bit (Read-only)
This bit indicates the Pass/Fail status following completion of the Local Data
Memory BIST sequence (indicated by assertion of BISTCDL).
A HIGH indicates Pass, a LOW indicates Fail.
Backplane Connection Memory Start BIST Sequence
Sequence enabled on LOW to HIGH transition.
Backplane Connection Memory BIST Sequence Completed (Read-only)
This bit must be polled - when HIGH, indicates completion of Backplane
Connection Memory BIST sequence.
Backplane Connection Memory Pass/Fail Bit (Read-only)
This bit indicates the Pass/Fail status following completion of the Backplane
Connection Memory BIST sequence (indicated by assertion of BISTCCB).
A HIGH indicates Pass, a LOW indicates Fail.
Local Connection Memory Start BIST Sequence
Sequence enabled on LOW to HIGH transition.
Zarlink Semiconductor Inc.
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Description
Data Sheet