ZL50051 ZARLINK [Zarlink Semiconductor Inc], ZL50051 Datasheet - Page 31

• Manufacturer Part Number: ZL50051
• Description: 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

9.0
As operation of the memory BIST will corrupt existing data, this test must only be initiated when the device is placed
“out-of-service” or isolated from live traffic.
The memory BIST mode is enabled through the microprocessor port (Section 13.7, “Memory BIST Register”).
Internal BIST memory controllers generate the memory test pattern (S-march) and control the memory test. The
memory test result is monitored through the Memory BIST Register.
10.0
The ZL50051/3 JTAG interface conforms to the IEEE 1149.1 standard. The operation of the boundary-scan circuit
shall be controlled by an external Test Access Port (TAP) Controller.
10.1
The Test Access Port (TAP) consists of four input pins and one output pin described as follows:
•
•
•
•
•
10.2
The ZL50051/3 implements the public instructions defined in the IEEE-1149.1 standard with the provision of an
Instruction Register and three Test Data Registers.
10.2.1
The JTAG interface contains a four bit instruction register. Instructions are serially loaded into the Instruction
Register from the TDi pin when the TAP Controller is in the shift-IR state. Instructions are subsequently decoded to
achieve two basic functions: to select the Test Data Register to operate while the instruction is current, and to
define the serial Test Data Register path to shift data between TDi and TDo during data register scanning. Please
refer to Figure 27 for JTAG test port timing.
Test Clock Input (TCK)
TCK provides the clock for the TAP Controller and is independent of any on-chip clock. TCK permits the
shifting of test data into or out of the Boundary-Scan register cells under the control of the TAP Controller in
Boundary-Scan Mode.
Test Mode Select Input (TMS)
The TAP controller uses the logic signals applied to the TMS input to control test operations. The TMS
signals are sampled at the rising edge of the TCK pulse. This pin in internally pulled to V
driven from an external source.
Test Data Input (TDi)
Depending on the previously applied data to the TMS input, the serial input data applied to the TDi port is
connected either to the Instruction Register or to a Test Data Register. Both registers are described in
Section 10.2, “TAP Registers”. The applied input data is sampled at the rising edge of TCK pulses. This pin
is internally pulled to V
Test Data Output (TDo)
Depending on the previously applied sequence to the TMS input, the contents of either the instruction
register or data register are serially shifted out towards the TDo. The data out of the TDo is clocked on the
falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDo output is
set to a high impedance state.
Test Reset (TRST)
TRST provides an asynchronous Reset to the JTAG scan structure. This pin is internally pulled high when
not driven from an external source. This pin MUST be pulled low for normal operation.
Memory Built-In-Self-Test (BIST) Mode
Test Access Port (TAP)
TAP Registers
JTAG Port
Test Instruction Register
DD_IO
when not driven from an external source.
Zarlink Semiconductor Inc.
ZL50051/3
31
DD_IO
Data Sheet
when not