AM79C901AJCT AMD [Advanced Micro Devices], AM79C901AJCT Datasheet - Page 53

• Manufacturer Part Number: AM79C901AJCT
• Description: HomePHY Single-Chip 1/10 Mbps Home Networking PHY
• Manufacturer: AMD [Advanced Micro Devices]

HPR24: HomePNA PHY Noise Control 2 Register (Register 24)
HPR25: HomePNA PHY Noise Statistics Register (Register 25)
Bits
15:8
Bits
15:8
7:0
7:0
Noise Attack
Reserved
Noise Level
Peak Level
Table 32. HPR24: HomePNA PHY Noise Control 2 Register (Register 24)
Table 33. HPR25: HomePNA PHY Noise Statistics Register (Register 25)
Name
Name
P R E L I M I N A R Y
Sets the attack characteristics of the NOISE
algorithm. High nibble sets number of noise events
needed to raise the NOISE level immediately, while
the low nibble is the number of noise events needed
to raise the level at the end of an 870 ms period.
Reads will produce undefined results.
This is the digital value of the SLICE_LVL_NOISE
output. It is effectively a measure of the noise level
on the wire and tracks noise by counting the
number of false triggers of the NOISE comparator
in an 800 ms window. When auto-adaptation is
enabled (bit 5 of the PHY_Control Register is
false), this register is updated with the current
NOISE count every 50 ns. When adaptation is
disabled, this register may be written to and is used
to generate both the SLICE_LVL_NOISE and
SLICE_LVL_DATA signals.
This is a measurement of the peak level of the last
valid (non-collision) AID received.
Am79C901A
Description
Description
Read/
Read/
Write
Write
R/W
R/W
R/W
R
Default
Default
Value
Value
(hex)
XX
FF
F4
03
53