AM79C850KCW AMD [Advanced Micro Devices], AM79C850KCW Datasheet - Page 47

• Manufacturer Part Number: AM79C850KCW
• Description: SUPERNET-R 3
• Manufacturer: AMD [Advanced Micro Devices]

Status Receive Parity Error Queue 2
SRPERRQ2 (bit 3)
This bit is set when there is parity error in the data
received in queue 2.
Status Receive Parity Error Queue 1
SRPERRQ2 (bit 2)
This bit is set when there is parity error in the data
received in queue 1.
Status Receive Queue 2 Unlocked
SRQUNLCK2 (bit 1)
This bit is set when the auto-unlock feature unlocks the
Receive Queue 2 lock due to buffer full condition. Once
the unlock threshold is crossed due the host read
operation, the SUPERNET 3 will clear the lock on the
receive queue 2 and enable the queue for further input.
Status Receive Queue 1 Unlocked
SRQUNLCK2 (bit 0)
This bit is set when the auto-unlock feature unlocks the
Receive Queue 1 lock due to buffer full condition. Once
the unlock threshold is crossed due the host read
operation, the SUPERNET 3 will clear the lock on the
receive queue 1 and enable the queue for further input.
The following bits are in ST3L (the lower half of ST3).
Reserved (bit 15–bit 8)
These bits are reserved for future use. Some of these
reserved bits may read zero or one and the user should
ignore these bits. The corresponding mask register bits
should be programmed to mask out the interrupts from
these bits.
Status Internal CAM Source Address Exact Match.
SICAMSAXACT (bit 7)
This bit when set indicates that the source address of
the incoming frame exactly matches an entry in the
internal CAM. This bit is useful for monitoring frame
reception and internal CAM operation.
Status Internal CAM Source Address Match
SICAMSAMAT (bit 6)
This bit when set indicates that the source address of
the incoming frame matches an entry in the internal
P R E L I M I N A R Y
SUPERNET 3
CAM based on the internal CAM match logic. This bit
is useful for monitoring frame reception and internal
CAM operation.
Status Internal CAM Destination Address Exact
Match
SICAMDAXACT (bit 5)
This bit when set indicates that the received frame DA
exactly matches an entry in the internal CAM. This bit is
useful for monitoring frame reception and internal
CAM operation.
Status Internal CAM Destination Address Match
SICAMDAMAT (bit 4)
This bit when set indicates that the received frame DA
matches an entry in the internal CAM based in the
internal CAM match logic. This bit is useful for
monitoring frame reception and internal CAM operation.
Reserved (bit 3)
This bit is reserved for future use. The bit may read zero
or one and the user should ignore this bit. The
corresponding mask register bit should be programmed
to mask out the interrupts from this bit.
Reserved (bit 2)
This bit is reserved for future use. The bit may read zero
or one and the user should ignore this bit. The
corresponding mask register bit should be programmed
to mask out the interrupts from this bit.
Status Physical Layer Controller BIST Done
PLC_BIST_DONE (bit 1)
This bit when set indicates that the PLC BIST
is complete.
Status Address Filter BIST Done
AF_BIST_DONE (bit 0)
This bit when set indicates that Address Filter (Internal
CAM) BIST is complete.
AMD
47