AM79C850KCW AMD [Advanced Micro Devices], AM79C850KCW Datasheet - Page 14

• Manufacturer Part Number: AM79C850KCW
• Description: SUPERNET-R 3
• Manufacturer: AMD [Advanced Micro Devices]

change in ring status has occurred. MINTR2 is deacti-
vated once either the lower or upper 16 bits of status
register 2 (ST2L or ST2U) are read. Once MINTR2 is
asserted, all 32 bits of status register 2 must be read in
order to enable any future interrupt on this pin.
MINTR3
Maskable Interrupt 3 (TTL output, open drain, high
impedance)
The MINTR3 output (active low) is an attention line to
the NP. MINTR3, when active, indicates an interrupt due
to one or more unmasked flags in status register 3. In
general, the active state of MINTR3 indicates that an
unmasked interrupt condition, a receive condition in the
second receive queue has occurred. MINTR3 is deacti-
vated once either the lower or upper 16 bits of status
register 3 (ST3L or ST3U) are read. Once MINTR3 is
asserted, all 32 bits of status register 3 must be read in
order to enable any future interrupt on this pin.
MINTR4
Maskable Interrupt 4 (TTL output, open drain, high
impedance)
The MINTR4 output (active low) is an attention line to
the NP. MINTR4, when active, indicates an interrupt due
to one or more unmasked flags in the PHY interrupt
event (INTR_EVENT) register. In general, the active
state of MINTR4 indicates that a change in PCM state
machine or timer expiration or counter overflow has
occurred. MINTR4 remains active until cleared by
reading the INTR_EVENT register.
When the MENSNGLINT (MDREG 3, bit 10) is set, the
SUPERNET 3 generates only one interrupt (MINTR4)
and the other interrupt lines (MINTR1, MINTR2, and
MINTR3) are not toggled. The SUPERNET 3 operates
in a vectored interrupt mode, i.e., a vector register is
read to determine which status register is the source of
the interrupt.
NPMEMRQ
Node Processor Memory Request (TTL input)
The input signal NPMEMRQ is a request by the node
processor to obtain control of buffer memory.
NPMEMACK
Node Processor Memory Access Acknowledge
(TTL output, high impedance)
This signal indicates that an NPMEMRQ has been
granted and that the NP now has control of buffer
memory (ADDR-bus, RD, WR, CSO, BDP, BD, and
BDTAG).
NPMEMRQ is active (due to a higher priority request),
the NP must release control of the bus within
two BMCLK periods after the NPMEMACK line
goes inactive.
14
AMD
If
NPMEMACK
is
forced
low
P R E L I M I N A R Y
while
SUPERNET 3
SUPERNET 3/Buffer Memory Interface
(56 Pins)
ADDR15–0
Buffer Memory Address (TTL output, high
impedance)
The 16-bit ADDR-bus provides the addresses that
access the buffer memory. The address selection
depends on the result of bus arbitration in the
SUPERNET 3. Each memory access lasts for two
BMCLK clock cycles and the address is valid for both of
these cycles. When buffer memory control has been
released to the NP, the ADDR bus is in the high-imped-
ance state.
Note: As long as the use of the buffer memory has not
been granted to the node processor or host (HSACK
and NPMEMACK not active), the SUPERNET 3 may
drive the address lines even though no control signals
are active.
BD31–0
Buffer Memory Data Bus (TTL input, output, high
impedance)
The 32-bit BD bus interfaces the SUPERNET 3 to the
buffer memory or any external logic using this bus.
These lines transfer data to and from the buffer memory
for the SUPERNET 3. These signals are synchronous
to BMCLK.
BDP3–0
Buffer Data Parity Bus (TTL input, output, high
impedance)
The BDP3–0 bus contains the four byte-parity lines for
the BD bus as shown in the following table:
Note: BD bus parity can be either even or odd, based on
the state of the parity bit (bit 12) in mode register
2 (MDREG2).
BDTAG
Buffer Data Tag Indication (TTL input, output, high
impedance)
In receive mode, this bit defines whether the information
on the BD bus is data (BDTAG = 0) or frame status
(BDTAG = 1). In transmit mode, when BDTAG = 1, it
indicates that the end of a frame has been reached, as
indicated by the presence of a tag bit in both the last long
BD-Bus Lines
BD7–0 and tag bit
BD15–8
BD23–16
BD31–24
Corresponding
Parity Lines
BDP1
BDP2
BDP3
BDP0