AM79C850KCW AMD [Advanced Micro Devices], AM79C850KCW Datasheet - Page 26

• Manufacturer Part Number: AM79C850KCW
• Description: SUPERNET-R 3
• Manufacturer: AMD [Advanced Micro Devices]

Transmit Command
The SUPERNET 3 provides a feature to control
transmission of frames from ASYNC1 queue in both
TAG and Modified TAG modes. This feature can be
enabled by programming the MENTRCMD (bit 14) in
mode register 3 (MDREG3). This feature, when en-
abled, would wait for the “Transmit Asynchronous
Queue1” command. This feature would be applicable
only to ASYNC1 queue. The SUPERNET 3 has to be in
initialize mode to enable the transmit command feature.
Once this is enabled the SUPERNET 3 will not transmit
from ASYNC1 queue unless a command in given by
the Node Processor. To disable this feature, the
SUPERNET 3 has to be in initialize or memory active
mode. The read pointer (RPXA1), write pointer
(WPXA1) and shadow write pointer (SWPXA1) are
under the control of the user. The frames to be
transmitted could be loaded by the host into the buffer
memory either by using the host request pins, or by
using NPDMA pins or by using the MARW and
MDR registers.
When using the host request pins, the SUPERNET 3
responds to the host request as in any mode, except that
the transmit threshold register value would be ignored.
IFPC would not monitor the frames being loaded into
buffer memory for memory full condition, buffer empty
condition etc. After the last data word and descriptor are
written to complete the frame, transmit command can be
issued to start transmission.
When NPMEMRQ pin is used by the NP the address
bus and memory control signal lines are placed in the
high-impedance state by the SUPERNET 3. This gives
the NP free access to load the buffer memory, however,
the frames must conform to the format defined. The NP
is also responsible in keeping track of Async 1 pointers
(WPXA1, RPXA1, LTDPA1) prior to issuing the
transmit command.
When the NP uses the MARW and MDR to load the
buffer memory, it first loads the MARW with the starting
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P R E L I M I N A R Y
SUPERNET 3
address of the frame. Then the MDRU is loaded from the
NP, followed by the MDRL. As soon as the second 16-bit
data word is loaded, SUPERNET 3 sets an internal
request to move the contents of the MDR to the buffer
memory. The MARW is incremented after the write
operation is completed. The NP could use the set tag
command in CMDREG2 to set the tag bit for the MDR
write cycle, however, the tag bit command is valid for
one NP write operation only.
After the complete frame(s) have been loaded for
transmission, the NP has to program the last transmit
descriptor pointer (LTDPA1) to be equal to the address
of the last descriptor written. Also, the ASYNC1 queue
(WPXA1) write pointer needs to be programmed to
LTDPA1 + 1. The SUPERNET 3 would assume that the
read pointer is at the correct address. The NP should
then give an instruction to SUPERNET 3 to transmit the
ASYNC1 queue. The SUPERNET 3 would transmit till
the read pointer (RPXA1) equals the last transmit
descriptor pointer (LTDPA1). The user could load
multiple frames before issuing the command. The NP
cannot issue more than one transmit command until the
SUPERNET 3 indicates the “End of transmit command”
status (STECMDA1) in status register 1 - upper (ST1U).
TDAT Loopback
The SUPERNET 3 provides a feature to control the
loopback of transmit datapath after the PLC (TDAT)
back to the receive data path of the PLC (RDAT). This
loopback path is enabled when MDREG3, bit 15
(MENTDLPBK) bit is set to logic “1”.
Mode Register 3 (MDREG3)
An additional 16-bit mode register 3 is provided. The
new features and modifications are enabled by the
setting of the bits in the MDREG3. By default, the
register bits are reset to zero. This register can only be
written when the SUPERNET 3 is in Initialize or Memory
Active modes.