ZL30101QDC ZARLINK [Zarlink Semiconductor Inc], ZL30101QDC Datasheet - Page 8

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ZL30101QDC

Manufacturer Part Number
ZL30101QDC
Description
T1/E1 Stratum 3 System Synchronizer
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
Pin Description (continued)
Pin #
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
OUT_SEL
C4/C65o
AV
AGND
AGND
AGND
AGND
Name
OSCo
C1.5o
OSCi
AV
AV
AV
GND
RST
V
NC
NC
NC
NC
NC
IC
IC
IC
CORE
DD
DD
DD
DD
Reset (Input). A logic low at this input resets the device. On power up, the RST pin
must be held low for a minimum of 300 ns after the power supply pins have reached
the minimum supply voltage. When the RST pin goes high, the device will transition
into a Reset state for 3 ms. In the Reset state all outputs will be forced into high
impedance.
Oscillator Master Clock (Output). For crystal operation, a 20 MHz crystal is connected
from this pin to OSCi. This output is not suitable for driving other devices. For clock
oscillator operation, this pin must be left unconnected.
Oscillator Master Clock (Input). For crystal operation, a 20 MHz crystal is connected
from this pin to OSCo. For clock oscillator operation, this pin must be connected to a
clock source.
Internal Connection. Leave unconnected.
Ground. 0 V.
No internal bonding Connection. Leave unconnected.
Positive Supply Voltage. +3.3 V
Output Selection (Input). This input selects the signals on the combined output clock
and frame pulse pins, see Table 2 on page 17.
Internal Connection. Connect this pin to ground.
Internal Connection. Connect this pin to ground.
Positive Analog Supply Voltage. +3.3 V
No internal bonding Connection. Leave unconnected.
No internal bonding Connection. Leave unconnected.
Clock 1.544 MHz (Output). This output is used in DS1 applications.
This clock output pad includes a Schmitt input which serves as a PLL feedback path;
proper transmission-line termination should be applied to maintain reflections below
Schmitt trigger levels.
Analog Ground. 0 V
Analog Ground. 0 V
Positive Analog Supply Voltage. +1.8 V
Positive Analog Supply Voltage. +3.3 V
Positive Analog Supply Voltage. +3.3 V
No internal bonding Connection. Leave unconnected.
No internal bonding Connection. Leave unconnected.
Analog Ground. 0 V
Analog Ground. 0 V
Clock 4.096 MHz or 65.536 MHz (Output). This output is used for ST-BUS operation at
2.048 Mbps, 4.096 Mbps or 65.536 MHz (ST-BUS 65.536 Mbps). The output frequency is
selected via the OUT_SEL pin.
Zarlink Semiconductor Inc.
ZL30101
8
DC
nominal.
Description
DC
DC
DC
DC
nominal.
nominal.
nominal.
nominal.
Data Sheet

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