ZL30101QDC ZARLINK [Zarlink Semiconductor Inc], ZL30101QDC Datasheet - Page 21

• Manufacturer Part Number: ZL30101QDC
• Description: T1/E1 Stratum 3 System Synchronizer
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

5.5
Frequency accuracy is defined as the absolute accuracy of an output clock signal when it is not locked to an
external reference, but is operating in a free running mode.
5.6
Holdover accuracy is defined as the absolute accuracy of an output clock signal, when it is not locked to an external
reference signal, but is operating using storage techniques. For the ZL30101, the storage value is determined while
the device is in Normal Mode and locked to an external reference signal.
5.7
Also referred to as capture range. This is the input frequency range over which the PLL must be able to pull into
synchronization.
5.8
This is the input frequency range over which the synchronizer must be able to maintain synchronization.
5.9
Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect
to an ideal signal. The given signal is typically the output signal. The ideal signal is of constant frequency and is
nominally equal to the value of the final output signal or final input signal. Another way of specifying the phase slope
is as the fractional change per time unit. For example; a phase slope of 61 µs/s can also be specified as 61 ppm.
5.10
TIE is the time delay between a given timing signal and an ideal timing signal.
5.11
MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a
particular observation period.
5.12
Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a
particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency.
Phase continuity applies to the output of the PLL after a signal disturbance due to a reference switch or a mode
change. The observation period is usually the time from the disturbance, to just after the synchronizer has settled to
a steady state.
5.13
This is the time it takes the PLL to frequency lock to the input signal. Phase lock occurs when the input signal and
output signal are aligned in phase with respect to each other within a certain phase distance (not including jitter).
Lock time is affected by many factors which include:
•
•
•
initial input to output phase difference,
initial input to output frequency difference,
PLL loop filter bandwidth,
Frequency Accuracy
Holdover Accuracy
Pull-in
Lock Range
Phase Slope
Maximum Time Interval Error (MTIE)
Time Interval Error (TIE)
Phase Continuity
Lock Time
Range
Zarlink Semiconductor Inc.
ZL30101
21
Data Sheet