ZL30101QDC ZARLINK [Zarlink Semiconductor Inc], ZL30101QDC Datasheet - Page 11

• Manufacturer Part Number: ZL30101QDC
• Description: T1/E1 Stratum 3 System Synchronizer
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Exceeding the thresholds of any of the monitors forces the corresponding REF_FAIL pin to go high. The single
cycle and coarse frequency failure flags force the DPLL into Holdover mode and feed a timer that disqualifies the
reference input signal when the failures are present for more than 2.5 s. The single cycle and coarse frequency
failures must be absent for 10 s to let the timer requalify the input reference signal as valid. Multiple failures of less
than 2.5 s each have an accumulative effect and will disqualify the reference eventually. This is illustrated in Figure
4.
When the incoming signal returns to normal (REF_FAIL=0), the DPLL returns to Normal mode with the output
signal locked to the input signal. Each of the monitors has a build-in hysteresis to prevent flickering of the
REF_FAIL status pin at the threshold boundaries. The precise frequency monitor and the timer do not affect the
mode (Holdover/Normal) of the DPLL.
REF0 /
REF1
current REF
REF_FAIL
HOLDOVER
timer
Reference Frequency
Precise Frequency
Coarse Frequency
Single Cycle
Detector
Monitor
Monitor
Monitor
2.5 s
Figure 4 - Behaviour of the Dis/Requalify Timer
Figure 3 - Reference Monitor Circuit
OR
10 s
Zarlink Semiconductor Inc.
SCM or CFM failure
ZL30101
dis/requalify
11
timer
OR
REF_DIS= reference disrupted.
This is an internal signal.
REF_DIS
Mode select
state machine
Data Sheet
HOLDOVER
REF_FAIL0 /
REF_FAIL1