ZL30101QDC ZARLINK [Zarlink Semiconductor Inc], ZL30101QDC Datasheet - Page 17

• Manufacturer Part Number: ZL30101QDC
• Description: T1/E1 Stratum 3 System Synchronizer
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

4.0
4.1
The loop filter settings can be selected through the BW_SEL pin, see Table 1. For the ZL30101 to be compliant with
Telcordia GR-1244-CORE Stratum 3, BW_SEL must be set low.
4.2
The output clock and frame pulses of the frequency synthesizers are available in two groups controlled by the
OUT_SEL input. Table 2 lists the supported combinations of output clocks and frame pulses.
4.3
The ZL30101 has three possible manual modes of operation; Normal, Holdover and Freerun. These modes are
selected with the mode select pins MODE_SEL1 and MODE_SEL0 as is shown in Table 3. Transitioning from one
mode to the other is controlled by an external controller.
4.3.1
Freerun mode is typically used when an independent clock source is required, or immediately following system
power-up before network synchronization is achieved.
In Freerun mode, the ZL30101 provides timing and synchronization signals which are based on the master clock
frequency (supplied to OSCi pin) only, and are not synchronized to the reference input signals.
Loop Filter Selection
Output Clock and Frame Pulse Selection
Modes of Operation
Control and Modes of Operation
Freerun Mode
BW_SEL
0
1
1
OUT_SEL
MODE_SEL1
0
1
0
0
1
1
Detected REF Frequency
8.192 MHz, 16.384 MHz
1.544 MHz, 2.048 MHz,
C1.5o, C2o, C16o, C32o, C65o
Table 2 - Clock and Frame Pulse Selection
MODE_SEL0
C1.5o, C2o, C4o, C8o, C16o
8 kHz
any
Generated Clocks
0
1
0
1
Table 1 - Loop Filter Settings
Table 3 - Operating Modes
Zarlink Semiconductor Inc.
ZL30101
17
Loop Filter Bandwidth
Normal (with automatic Holdover)
reserved (must not be used)
922 Hz
1.8 Hz
58 Hz
Holdover
Generated Frame Pulses
Freerun
Mode
F16o, F32o, F65o
F4o, F8o, F16o
Phase Slope Limiting
9.5 ms /s
9.5 ms /s
61 µs/s
Data Sheet