ADP2116-EVALZ AD [Analog Devices], ADP2116-EVALZ Datasheet - Page 6

• Manufacturer Part Number: ADP2116-EVALZ
• Description: Configurable, Dual 3 A/Single 6 A, Synchronous, Step-Down DC-to-DC Regulator
• Manufacturer: AD [Analog Devices]

ADP2116
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
Mnemonic
GND
COMP1
FREQ
SCFG
SYNC/CLKOUT
OPCFG
COMP2
VDD
FB2
V2SET
SS2
PGOOD2
EN2
Description
Ground for the Internal Analog and Digital Circuits. Connect GND to the signal/analog ground plane before connecting
to the power ground.
Error Amplifier Output for Channel 1. Connect a series RC network from COMP1 to GND to compensate the control
loop of Channel 1. For multiphase operation, tie COMP1 and COMP2 together.
Frequency Select Input. Connect this pin through a resistor to GND to set the appropriate switching frequency
(see Table 5).
Synchronization Configuration Input. SCFG configures the SYNC/CLKOUT pin as an input or output. Tie this pin to
VDD to configure SYNC/CLKOUT as an output. Tie this pin to GND to configure SYNC/CLKOUT as an input.
External Synchronization Input/Internal Clock Output. This bidirectional pin is configured with the SCFG pin (see the
Pin 4 description for details). When this pin is configured as an output, a buffered clock of twice the switching frequency
with a phase shift of 90° is available on this pin. When configured as an input, this pin accepts an external clock to which
the converters are synchronized. The frequency select resistor, mentioned in the description of Pin 3, must be selected
to be close to the expected switching frequency for stable operation (see the Setting the Oscillator Frequency section).
Operation Configuration Input. Connect this pin to VDD or through a resistor to GND to set the system mode of
operation according to Table 7. This pin can be used to select a peak current limit for each power channel and to
enable or disable the pulse skip mode.
Error Amplifier Output for Channel 2. Connect a series RC network from COMP2 to GND to compensate the control
loop of Channel 2. For multiphase operation, tie COMP1 and COMP2 together.
Power Supply Input. The power source for the ADP2116 internal circuitry. Connect VDD and VINx with a 10 Ω resistor
as close as possible to the ADP2116. Bypass VDD to GND with a 1 μF or greater capacitor.
Feedback Voltage Input for Channel 2. For the fixed output voltage option, connect FB2 to V
output voltage option, connect this pin to a resistor divider between V
adjustable output voltage option is 0.6 V. With multiphase configurations, the FB2 and FB1 pins should be tied
together and then connected to V
Output Voltage Set Pin for Channel 2. To select a fixed output voltage option (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V)
for V
for V
output voltage desired.
Soft Start Input for Channel 2. Place a capacitor from SS2 to GND to set the soft start period. A 10 nF capacitor
sets a 1 ms soft start period. For multiphase configuration, connect SS2 to SS1.
Open-Drain Power-Good Output for Channel 2. Place a 100 kΩ pull-up resistor to VDD or to any other voltage that is
5.5 V or less; PGOOD2 is held low when Channel 2 is out of regulation.
Enable Input for Channel 2. Drive EN2 high to turn on the Channel 2 converter; drive EN2 low to turn off the Channel 2
converter. Tie EN2 to VDD for startup with VDD. When using a multiphase configuration, connect EN2 to EN1.
OUT2
OUT2
, connect this pin through a resistor to GND (see Table 4 for details). To select an adjustable output voltage
, connect this pin to GND through an 82 kΩ resistor or tie this pin directly to VDD depending on the
SYNC/CLKOUT
NOTES
1. CONNECT THE EXPOSED THERMAL PAD TO THE
SIGNAL/ANALOG GROUND PLANE.
COMP1
OPCFG
COMP2
FREQ
SCFG
GND
VDD
Figure 3. Pin Configuration
1
2
3
4
5
6
7
8
OUT
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.
THERMAL PAD
(Not to Scale)
ADP2116
TOP VIEW
24 SW1
23 SW2
22 PGND1
21 PGND2
20 PGND3
19 PGND4
18 SW3
17 SW4
OUT2
and GND. The reference voltage for the
OUT2
. For the adjustable