ADP2116-EVALZ AD [Analog Devices], ADP2116-EVALZ Datasheet - Page 20

• Manufacturer Part Number: ADP2116-EVALZ
• Description: Configurable, Dual 3 A/Single 6 A, Synchronous, Step-Down DC-to-DC Regulator
• Manufacturer: AD [Analog Devices]

ADP2116
THEORY OF OPERATION
The ADP2116 is a high efficiency, dual, fixed switching frequency,
synchronous, step-down dc-to-dc converter with flex mode
architecture, which is the Analog Devices, Inc., proprietary version
of peak current mode control architecture. The device operates
over an input voltage range of 2.75 V to 5.5 V. Each output channel
can provide an adjustable output as low as 0.6 V and deliver up
to 3 A of load current. When the output channels are tied together,
they operate 180° out of phase to deliver up to 6 A of load current.
The integrated high-side, P-channel power MOSFET and the
low-side, N-channel power MOSFET yield high efficiency at
medium to heavy loads. Pulse skip mode is available for improved
efficiency at light loads. With a high switching frequency (up to
2 MHz) and integrated power switches, the ADP2116 is optimized
to deliver high performance in a small package for power manage-
ment solutions.
The ADP2116 also includes undervoltage lockout (UVLO) with
hysteresis, soft start, and power good, as well as protection features
such as output short-circuit protection and thermal shutdown.
The output voltages, current limits, switching frequency, pulse
skip operation, and soft start time are externally programmable
with tiny resistors and capacitors.
CONTROL ARCHITECTURE
The ADP2116 consists of two step-down dc-to-dc converters that
deliver regulated output voltages, V
by modulating the duty cycle at which the internal high-side,
P-channel power MOSFET and the low-side, N-channel power
MOSFET are switched on and off.
In steady-state operation, the output voltage V
sensed on the corresponding feedback pin, FB1 or FB2, and
attenuated in proportion to the selected output voltage on the
V1SET or V2SET pin. An error amplifier integrates the error
between the feedback voltage and the reference voltage (V
0.6 V) to generate an error voltage at the COMP1 or COMP2 pin.
The valley inductor current is sensed by a current-sense ampli-
fier when the low-side, N-channel MOSFET is on. An internal
oscillator turns off the low-side, N-channel MOSFET and turns on
the high-side, P-channel MOSFET at a fixed switching frequency.
When the high-side, P-channel MOSFET is enabled, the valley
inductor current information is added to an emulated ramp signal
and compared to the error voltage by the PWM comparator.
The output of the PWM comparator modulates the duty cycle
by adjusting the trailing edge of the PWM pulse that switches the
power devices. Slope compensation is programmed internally into
the emulated ramp signal and automatically selected, depending
on the input voltage, output voltage, and switching frequency.
This prevents subharmonic oscillations for greater than 50%
duty cycle operation.
OUT1
and V
OUT2
OUT1
(see Figure 1),
or V
OUT2
REF
is
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=
Control logic with the anti-shoot-through circuit monitors and
adjusts the low-side and high-side driver outputs to ensure break-
before-make switching. This monitoring and control prevents
cross-conduction between the internal high-side, P-channel power
MOSFET and the low-side, N-channel power MOSFET.
UNDERVOLTAGE LOCKOUT (UVLO)
The UVLO threshold is 2.65 V when V
2.47 V when V
the converter from turning off and on repeatedly in response to
changing load conditions during a slow voltage transition on
VDD that is close to the 2.75 V minimum operational level.
ENABLE/DISABLE CONTROL
The EN1 and EN2 pins are used to independently enable or
disable Channel 1 and Channel 2, respectively. Drive ENx high
to turn on the corresponding channel of the ADP2116. Drive
ENx low to turn off the corresponding channel of the ADP2116,
reducing the input current to less than 1 μA. To force a channel
to start automatically when input power is applied, connect the
corresponding ENx pin to VDD. When shut down, the ADP2116
channels discharge the soft start capacitor, causing a new soft
start cycle every time the converters are reenabled.
SOFT START
The ADP2116 soft start feature allows the output voltage to ramp
up in a controlled manner, eliminating output voltage overshoot
during startup. Soft start begins after the undervoltage lockout
threshold is exceeded and an enable pin, EN1 or EN2, is pulled
high to greater than 2.0 V. External capacitors to ground are
required on both the SS1 and SS2 pins. Each regulating channel
has its own soft start circuit. When the converter powers up and
is enabled, the internal 6 μA current source charges the external
soft start capacitor, establishing a voltage ramp slope at the SS1
or SS2 pin, as shown in Figure 58. The soft start time ends when
the soft start ramp voltage exceeds the internal reference of 0.6 V.
1
2
4
3
CH1 5.0V
CH3 5.0V
V
EN
SS
SW
OUT
DD
B
B
W
W
is decreasing. The 180 mV hysteresis prevents
CH2 1.0V
CH4 2.0V
Figure 58. Soft Start
B
B
W
W
100ns/pt
M1.0ms
DD
is increasing and
A CH1
2.4V