ADP2116-EVALZ AD [Analog Devices], ADP2116-EVALZ Datasheet - Page 24

• Manufacturer Part Number: ADP2116-EVALZ
• Description: Configurable, Dual 3 A/Single 6 A, Synchronous, Step-Down DC-to-DC Regulator
• Manufacturer: AD [Analog Devices]

ADP2116
SETTING THE OSCILLATOR FREQUENCY
The ADP2116 channels can be set to operate in one of three
preset switching frequencies: 300 kHz, 600 kHz, or 1.2 MHz.
For 300 kHz operation, connect the FREQ pin to GND. For
600 kHz or 1.2 MHz operation, connect a resistor between the
FREQ pin and GND (see Table 5).
Table 5. Oscillator Frequency Setting
R
0 Ω to GND
8.2 kΩ to GND
27 kΩ to GND
The choice of the switching frequency depends on the required dc-
to-dc conversion ratio and the need for small external components.
In addition, due to the minimum on and off times required for
current sensing and robust operation, the frequency is limited
by the minimum and maximum controllable duty cycle (see
Figure 64).
For small, area-limited power solutions, use of higher switching
frequencies is recommended. For single-output, multiphase
applications that operate at close to 50% duty cycle, use a 1.2 MHz
switching frequency to minimize crosstalk between the phases.
SYNCHRONIZATION AND CLKOUT
The ADP2116 can be configured to output an internal clock or
to synchronize to an external clock at the SYNC/CLKOUT pin.
The SYNC/CLKOUT pin is a bidirectional pin configured by
the SCFG pin (see Table 6).
Table 6. SYNC/CLKOUT Configuration Setting
SCFG
GND
VDD
The converter switching frequency, f
nization frequency, f
FREQ
± 5%
100
90
80
70
60
50
40
30
20
10
0
200
Figure 64. Duty Cycle Working Limits
400
MAXIMUM LIMIT
MINIMUM LIMIT, V
MINIMUM LIMIT, V
MINIMUM LIMIT, V
SYNC
SWITCHING FREQUENCY (kHz)
SYNC/CLKOUT
Input (SYNC)
Output (CLKOUT)
or f
600
CLKOUT
IN
IN
IN
f
300
600
1200
= 2.75V
= 3.3V
= 5.5V
, as shown in Equation 4,
SW
SW
800
(kHz)
, is half of the synchro-
1000
1200
Rev. 0 | Page 24 of 36
irrespective of whether SYNC/CLKOUT is configured as an
input or an output.
An external clock can be applied to the SYNC/CLKOUT pin when
configured as an input to synchronize multiple ADP2116 devices
to the same external clock. The f
which produces f
When synchronizing to an external clock, the switching frequency
(f
quency by appropriately terminating the FREQ pin (see Table 5).
The ADP2116 can also be configured to output a clock signal on
the SYNC/CLKOUT pin that can be used to synchronize multiple
ADP2116 devices (see Figure 66). The CLKOUT signal is 90°
phase shifted relative to the internal clock of the channels so
that the master ADP2116 and the slave channels are out of
phase (see Figure 67 for additional information).
SW
TO OTHER ADP2116 DEVICES
f
EXTERNAL CLOCK (2.4MHz)
) must be set close to half of the expected external clock fre-
SYNC
f
SYNC
Figure 65. Synchronization with External Clock (f
4
3
1
Figure 66. ADP2116 to Synchronize with Another ADP2116
CH1 5.0V
CH3 5.0V
(f
( or f
SW
= 600 kHz; the SCFG Pin of the Master Is Tied to VDD)
CLKOUT
SCFG
SYNC
SCFG
SYNC
f
SW
(
B
B
(
SYNC
f
f
W
W
SW
ADP2116
ADP2116
SW
8.2kΩ
27kΩ
in the 200 kHz to 2 MHz range (see Figure 65).
Figure 67. CLKOUT Waveforms
) = 2 × f
FREQ
=
CH4 5.0V
FREQ
=
= 2 ×
f
f
SYNC
SYNC
INTERNAL CLKOUT
f
SW
/2)
/2)
CHANNEL 1 SW
CHANNEL 2 SW
VDD
SW
VDD
B
W
M1.0µs
SYNC
TO OTHER ADP2116 DEVICES
range is 400 kHz to 4 MHz,
SCFG
CLKOUT
SCFG
SYNC
(
f
CLKOUT
(
f
ADP2116
ADP2116
A CH4
SW
8.2kΩ
27kΩ
FREQ
FREQ
=
SW
f
= 2 ×
SYNC
= 1.2 MHz)
3.00V
/2)
f
SW
VDD
VDD
)
V
V
IN
IN
(4)