ADP2116-EVALZ AD [Analog Devices], ADP2116-EVALZ Datasheet - Page 21

• Manufacturer Part Number: ADP2116-EVALZ
• Description: Configurable, Dual 3 A/Single 6 A, Synchronous, Step-Down DC-to-DC Regulator
• Manufacturer: AD [Analog Devices]

The capacitance value of the soft start capacitor defines the soft
start time, t
where:
V
I
C
If the output voltage, V
Channel 1 or Channel 2, respectively, the control logic prevents
inductor current reversal by keeping the power MOSFETs turned
off until the soft start voltage ramp at SS1 or SS2 reaches the
precharged output voltage on V
POWER GOOD
The ADP2116 features open-drain power-good outputs (PGOOD1
and PGOOD2) that indicate when the converter output voltage
is within regulation. The power-good signal transitions low
immediately when the corresponding channel is disabled.
The power-good circuitry monitors the output voltage on the FB1
or FB2 pin and compares it to the rising and falling thresholds
SS
REF
SS
is the soft start current, 6 μA.
is the soft start capacitor value.
is the internal reference voltage, 0.6 V.
V
1
2
4
3
t
REF
SS
CH1 5.0V
CH3 5.0V
V
=
EN1
SW1, SW2
OUT1
SS1
SS
Figure 59. Soft Start with a Precharged Output
, based on
C
I
SS
SS
B
B
W
W
CH2 1.0V
CH4 500mV
OUT1
or V
B
B
W
W
OUT2
M200µs 50MS/s
20ns/pt
FB1
, is precharged prior to enabling
or V
UNDERVOLTAGE
116%
100%
FB2
92%
(see Figure 59).
A CH1
V
OUT
RISING
PGOOD1/PGOOD2
Figure 60. PGOOD1/PGOOD2 Thresholds
2.4V
POWER
GOOD
Rev. 0 | Page 21 of 36
(1)
OVERVOLTAGE
specified in Table 1. If the rising output voltage (V
exceeds 116% of the target output voltage (V
the PGOOD1 or PGOOD2 pin is held low. The PGOOD1 or
PGOOD2 pin continues to be held low until the falling output
voltage returns to 108% of the target value.
If the output voltage drops below 84% of the target output voltage,
the corresponding PGOOD1 or PGOOD2 pin is held low. The
PGOOD1 or PGOOD2 pin continues to be held low until the
output voltage rises to within 92% of the target output voltage.
The PGOOD1 or PGOOD2 pin is then released, signaling that
the output voltage is within the power-good window.
The power-good thresholds are shown in Figure 60. The PGOOD1
and PGOOD2 outputs also sink current if an overtemperature
condition is detected. Use these outputs as logic power-good
signals by connecting the pull-up resistor from PGOOD1 or
PGOOD2 to VDD. If the power-good function is not used, the
pins can be left floating.
PULSE SKIP MODE
The ADP2116 has built-in pulse skip circuitry that turns on
during light loads, switching only as necessary to maintain the
output voltage within regulation. This allows the converter to
maintain high efficiency during light load operation by reducing
the switching losses. The pulse skip mode can be selected by
configuring the OPCFG pin as indicated in Table 7. In pulse
skip mode, when the output voltage dips below regulation, the
ADP2116 enters PWM mode for a few oscillator cycles to increase
the output voltage so that it is within regulation. During the wait
time between bursts, both power switches are off, and the output
capacitor supplies all of the load current. Because the output voltage
dips and recovers occasionally, the output voltage ripple in this
mode is larger than the ripple in the PWM mode of operation.
If the converter is configured to operate in forced PWM mode
(by selecting this configuration using the OPCFG pin), the device
operates with a fixed switching frequency, even at light loads.
V
POWER
OUT
GOOD
FALLING
UNDERVOLTAGE
108%
100%
84%
OUT1SET
ADP2116
OUT1
or V
or V
OUT2SET
OUT2
),
)