ADP2116-EVALZ AD [Analog Devices], ADP2116-EVALZ Datasheet - Page 22

• Manufacturer Part Number: ADP2116-EVALZ
• Description: Configurable, Dual 3 A/Single 6 A, Synchronous, Step-Down DC-to-DC Regulator
• Manufacturer: AD [Analog Devices]

ADP2116
HICCUP MODE CURRENT LIMIT
The ADP2116 features a hiccup mode current-limit implemen-
tation. When the peak inductor current exceeds the preset current
limit for more than eight consecutive clock cycles, the hiccup
mode current-limit condition occurs. The channel then goes to
sleep for 6.8 ms (at a 600 kHz switching frequency), which is
enough time for the output to be discharged and the average
power dissipation to be reduced. After the 6.8 ms elapses, the
channel wakes up with a soft start period (see Figure 61). If the
current-limit condition is subsequently triggered, the channel again
goes to sleep and wakes up after 6.8 ms. The current limits for
the two channels are programmed by configuring the OPCFG pin
(see Table 7). For the 3 A/3 A option, the output current limit is
set to 4.5 A per output. For the 3 A/2 A option, the current limits
are set to 4.5 A and 3.3 A for V
THERMAL OVERLOAD PROTECTION
The ADP2116 has an internal temperature sensor that monitors
the junction temperature. High current going into the switches
or a hot printed circuit board (PCB) can cause the junction
temperature of the ADP2116 to rise rapidly. When the junction
temperature reaches approximately 150°C, the ADP2116 goes
into thermal shutdown and the converter is turned off. When
the junction temperature cools to less than 125°C, the ADP2116
resumes normal operation after the soft start sequence.
4
2
3
CH3 5.0V
B
W
CH2 1.0V
CH4 2.0A
Figure 61. Hiccup Mode
INDUCTOR
CURRENT
V
Ω
SW
OUT
B
B
W
W
OUT1
200ns/pt
M2ms 5MS/s
and V
OUT2
A CH4
, respectively.
1.72A
Rev. 0 | Page 22 of 36
MAXIMUM DUTY CYCLE OPERATION
As the input voltage drops and approaches the output voltage,
the ADP2116 smoothly transitions to maximum duty cycle
operation, with the low-side, N-channel MOSFET switched on
for the minimum off time. In maximum duty cycle operation,
the output voltage dips below regulation because the output
voltage is the product of the input voltage and the maximum
duty cycle limitation. The maximum duty cycle limit is a function
of the switching frequency and the input voltage, as shown in
Figure 64.
SYNCHRONIZATION
The ADP2116 can be synchronized to an external clock such
that the two channels operate at a switching frequency that is
half of the input synchronization clock. The SYNC/CLKOUT
pin can be configured as an input SYNC pin or an output
CLKOUT pin through the SCFG pin, as detailed in Table 6.
Through the input SYNC pin, the ADP2116 can be synchronized
to an external clock such that the two channels switch at half
the external clock frequency and are 180° out of phase. Through
the output CLKOUT pin, the ADP2116 provides an output clock
that is twice the switching frequency of the channels and 90°
out of phase. Therefore, a single ADP2116 configured for the
CLKOUT option acts as the master converter and provides an
external clock for all other dc-to-dc converters (including other
ADP2116 devices). These other converters are configured as
slaves that accept an external clock and synchronize to it. This clock
distribution approach synchronizes all dc-to-dc converters in the
system and prevents beat harmonics that can lead to EMI issues.
The ADP2116 is optimized to power high performance signal
chain circuits. The slew rate of the switch node is controlled by
the size of the driver devices. Fast slewing of the switch node is
desirable to minimize transition losses but can, in turn, lead to
serious EMI issues due to parasitic inductance. To minimize
EMI generation, the slew rate of the drivers is optimized such
that the ADP2116 can match the performance of low dropout
regulators in supplying sensitive signal chain circuits while also
providing excellent power efficiency.