M58LT128HSB8ZA6 NUMONYX [Numonyx B.V], M58LT128HSB8ZA6 Datasheet - Page 88

• Manufacturer Part Number: M58LT128HSB8ZA6
• Manufacturer: NUMONYX [Numonyx B.V]

Common Flash Interface
88/110
Table 39.
1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank regions. There are two bank regions, see
(P+30)h = 13Ah
(P+31)h = 13Bh
M58LT128HST (top)
Offset
Bank and Erase Block region 1 information (continued)
Data
01h
03h
(P+30)h = 13Ah
(P+31)h = 13Bh
(P+32)h = 13Ch
(P+33)h = 13Dh
(P+34)h = 13Eh
(P+35)h = 13Fh
(P+36)h = 140h
(P+37)h = 141h
(P+38)h = 142h
(P+39)h = 143h
M58LT128HSB
Offset
(bottom)
Data
01h
03h
06h
00h
00h
02h
64h
00h
01h
03h
Table 29
Bank region 1 (Erase Block Type 1): bits per cell,
internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
Bank region 1 (Erase Block Type 1): Page mode
and Synchronous mode capabilities
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
Bank region 1 Erase Block Type 2 Information
Bits 0-15: n+1 = number of identical size Erase
Blocks
Bits 16-31: n×256 = number of bytes in Erase
Block region
Bank region 1 (Erase Block Type 2)
Minimum Block Erase cycles × 1000
Bank regions 1 (Erase Block Type 2): BIts per
cell, internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
Bank region 1 (Erase Block Type 2): Page mode
and Synchronous mode capabilities
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
to
Table
30.
M58LT128HST, M58LT128HSB
Description