ATAM894X-TNQY ATMEL [ATMEL Corporation], ATAM894X-TNQY Datasheet - Page 85

• Manufacturer Part Number: ATAM894X-TNQY
• Description: 8k-flash Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

7.1.1.1
7.1.2
7.1.2.1
7.1.2.2
7.1.2.3
4679D–4BMCU–05/05
EEPROM
Control Byte Format
EEPROM - Operating Modes
Write Operations
Acknowledge Polling
The EEPROM has a size of 2
and write data to and from the EEPROM the serial interface must be used. The interface sup-
ports one and two byte write accesses and one to n-byte read accesses to the EEPROM.
The operating modes of the EEPROM are defined via the control byte. The control byte contains
the row address, the mode control bits and the read/not-write bit that is used to control the direc-
tion of the following transfer. A '0' defines a write access and a '1' a read access. The five
address bits select one of the 32 rows of the EEPROM memory to be accessed. For all
accesses the complete 16-bit word of the selected row is loaded into a buffer. The buffer must
be read or overwritten via the serial interface. The two mode control bits C
which order the accesses to the buffer are performed: High byte – low byte or low byte – high
byte. The EEPROM also supports auto increment and auto decrement read operations. After
sending the start address with the corresponding mode, consecutive memory cells can be read
row by row without transmission of the row addresses.
Two special control bytes enable the complete initialization of EEPROM with '0' or with '1'.
The EEPROM permits 8-bit and 16-bit write operations. A write access starts with the START
condition followed by a write control byte and one or two data bytes from the master. It is com-
pleted via the STOP condition from the master after the acknowledge cycle.
The programming cycle consists of an erase cycle (write “zeros”) and the write cycle (write
“ones”). Both cycles together take about 10 ms.
If the EEPROM is busy with an internal write cycle, all inputs are disabled and the EEPROM will
not acknowledge until the write cycle is finished. This can be used to detect the end of the write
cycle. The master must acknowledge polling by sending a start condition followed by the control
byte. If the device is still busy with the write cycle, it will not return an acknowledge and the mas-
ter has to generate a stop condition or perform further acknowledge polling sequences. If the
cycle is complete, it returns an acknowledge and the master can proceed with the next read or
write cycle.
Start
Start
A4
Control byte
A3
EEPROM Address
A2
Ackn
512 bits and is organized as 32 x 16-bit matrix each. To read
A1
Data byte
A0
Mode Control Bits
Ackn
C1
Data byte
C0
NWrite
Read/
R/NW
1
ATAM894
and C
Ackn
2
define in
Ackn
Stop
85