ATAM894X-TNQY ATMEL [ATMEL Corporation], ATAM894X-TNQY Datasheet
ATAM894X-TNQY
Related parts for ATAM894X-TNQY
ATAM894X-TNQY Summary of contents
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Features • 8-bit EEPROM • EEPROM Programmable Options • Read Protection for the EEPROM Program Memory • 256 4-bit RAM • 16-bit Data EEPROM • Seven External/Internal Interrupt Sources • Eight Hardware and Software ...
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Pin Configuration Figure 2-1. Pinning SSO24 Package Table 2-1. Pin Description Pin Symbol Type Function 1 NC – Not connected 2 NC – Not connected 3 VDD – Supply voltage 4 BP40 I/O Bi-directional I/O line of Port 4.0 ...
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Table 2-1. Pin Description (Continued) Pin Symbol Type Function 19 BP41 I/O Bi-directional I/O line of Port 4.1 20 BP42 I/O Bi-directional I/O line of Port 4.2 T2O Timer 2 output 21 BP43 I/O Bi-directional I/O line of Port 4.3 ...
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Reset Function During each reset (power-on or brown-out) the configuration register is reset and reloaded with the data from the configuration memory. This leads to a slightly different behavior compared to the ROM versions. Both devices switch their I/Os ...
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Components of MARC4 Core The core contains ROM, RAM, ALU, program counter, RAM address registers, instruction decoder and interrupt controller. The following sections describe each functional block in more detail. 5.2.1 Program Memory The program memory (EEPROM) is electrically ...
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Expression Stack The 4-bit wide expression stack is addressed with the expression Stack Pointer (SP). All arith- metic, I/O and memory reference operations take their operands from, and return their results to the expression stack. The MARC4 performs the ...
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Figure 5-4. 5.2.3.2 ROM Banking Register (RBR) The ROM banking register is a 4-bit register whereby the ATAM894 only uses 2 bit. This register indicates which ROM bank is presently being addressed. The RBR is accessed with a standard qFORTH ...
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RAM Address Registers (X and Y) The X and Y registers are used to address any 4-bit item in the RAM. A fetch operation moves the addressed nibble onto the TOS. A store operation moves the TOS to the ...
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Figure 5-5. 5.2.5 I/O Bus The I/O ports and the registers of the peripheral modules are I/O mapped. All communication between the core and the on-chip peripherals takes place via the I/O bus and the associated I/O control. With the ...
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Interrupt Processing For processing the eight interrupt levels, the MARC4 includes an interrupt controller with two 8-bit wide “interrupt pending” and “interrupt active” registers. The interrupt controller samples all interrupt requests during every non-I/O instruction cycle and latches these ...
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Table 5-1. Interrupt Priority Table Interrupt Priority INT0 Lowest INT1 | INT2 | INT3 | INT4 | INT5 | INT6 INT7 Highest Table 5-2. Hardware Interrupts Interrupt Register INT1 P5CR INT2 INT3 INT4 T2CM T3CM1 INT5 T3CM2 INT6 P5CR INT7 ...
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Master Reset The master reset forces the CPU into a well-defined condition unmaskable and is activated independent of the current program state. It can be triggered by either initial supply power-up, a short collapse of the power ...
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A power-on reset pulse is generated brown-out reset pulse is generated when V values for the brown-out voltage threshold are programmable via the BOT bit in the SC register. When the controller runs in the upper supply ...
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Figure 5-9. 5.4.1 Voltage Monitor Control/ Status Register VMC: Write VMST: Read VM2: V oltage monitor M ode bit 2 VM1: V oltage monitor M ode bit 1 VM0: V oltage monitor M ode bit 0 Table 5-3. VM2 1 ...
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VIM VMS Figure 5-10. Internal Supply Voltage Supervisor Figure 5-11. External Input Voltage Supervisor 5.5 Clock Generation 5.5.1 Clock Module The ATAM894 contains a clock module with 4 different internal oscillator types: two RC-oscilla- tors, one 4-MHz crystal oscillator and ...
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The clock module is programmable via software with the clock management register (CM) and the system configuration register (SC). The required oscillator configuration can be selected with the OS1 bit and the OS0 bit in the SC register. A programmable ...
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Oscillator Circuits and External Clock Input Stage The ATAM894 series consists of four different internal oscillators: two RC-oscillators, one 4-MHz crystal oscillator, one 32-kHz crystal oscillator and one external clock input stage. 5.5.2.1 RC-oscillator 1 Fully Integrated For timing ...
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Table 5-5. 5.5.2.3 RC-oscillator 2 with External Trimming Resistor The RC-oscillator high resolution trimmable oscillator whereby the oscillator frequency can be trimmed with an external resistor between OSC1 and V lator 2 frequency can be maintained stable ...
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Figure 5-17. Ceramic Resonator Note: 5.5.2.5 32-kHz Oscillator Some applications require long-term time keeping or low resolution timing. In this case, an on-chip, low power 32-kHz crystal oscillator can be used to generate both the SUBCL and the SYSCL. In ...
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Clock Management Register (CM) CM: NSTOP CCS CSS1 CSS0 Table 5-6. 5.5.3.2 System Configuration Register (SC) SC: write BOT OS1 OS0 ATAM894 20 Bit 3 Bit 2 Bit 1 NSTOP CCS CSS1 Not STOP peripheral clock NSTOP = 0, ...
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Table 5-7. Mode Note: 5.6 Power-down Modes The sleep mode is a shut-down condition which is used to reduce the average system power consumption in applications where the microcontroller is not fully utilized. In this mode, ...
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Peripheral Modules 6.1 Addressing Peripherals Accessing the peripheral modules takes place via the I/O bus (see instructions allow direct addressing I/O modules. A dual register addressing scheme has been adopted to enable direct addressing of ...
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Table 6-1. Peripheral Addresses Port Address Name 1 P1DAT 2 P2DAT Auxiliary P2CR 3 SC CWD Auxiliary CM 4 P4DAT Auxiliary P4CR 5 P5DAT Auxiliary P5CR 6 P6DAT Auxiliary P6CR 7 T12SUB Subport address 0 T2C 1 T2M1 2 T2M2 ...
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Bi-directional Ports With the exception of Port 1 and Port 6, all other ports (2, 4 and 5) are 4 bits wide. Port 1 and Port 6 have a data width of 2 bits (bit 0 and bit 3). ...
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Figure 6-2. 6.2.2 Bi-directional Port 2 As all other bi-directional ports, this port includes a bit-wise-programmable Control Register (P2CR), which enables the individual programming of each port bit as input or output. It also opens up the possibility of reading ...
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Figure 6-3. 6.2.2.1 Port 2 Data Register (P2DAT) P2DAT Note: 6.2.2.2 Port 2 Control Register (P2CR) P2CR Note: Table 6-2. Code ...
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Bi-directional Port 5 As all other bi-directional ports, this port includes a bit-wise-programmable Control Register (P5CR), which allows the individual programming of each port bit as input or output. It also opens up the possibility of reading the pin ...
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Port 5 Data Register (P5DAT) P5DAT 6.2.3.2 Port 5 Control Register (P5CR) Byte Write P5CR P5xM2, P5xM1 – Port 5x Interrupt Mode/Direction Code Table 6-3. Port 5 Control Register Auxiliary Address: '5'hex First Write Cycle Code ...
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Figure 6-6. 6.2.4.1 Port 4 Data Register (P4DAT) P4DAT 6.2.4.2 Port 4 Control Register (P4CR) Byte Write P4CR P4xM2, P4xM1 4679D–4BMCU–05/05 Bi-directional Port 4 and Port 6 I/O Bus Intx PxMRy PIn POut I/O Bus D Q PxDATy S Master ...
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Table 6-4. Port 4 Control Register Auxiliary Address: '4'hex First Write Cycle Code Function BP40 in input mode BP40 in output mode BP40 enable ...
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Universal Timer/Counter/ Communication Module (UTCM) The Universal Timer/counter/Communication Module (UTCM) consists of three timers (Timer 1,Timer 2, Timer 3) and a Synchronous Serial Interface (SSI). • Timer interval timer that can be used to generate periodic ...
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Timer 1 The Timer interval timer which can be used to generate periodic interrupts and as pres- caler for Timer 2, Timer 3, the serial interface and the watchdog function. The Timer 1 consists of a ...
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Figure 6-9. T1C1 register CL1 6.3.1.1 Timer 1 Control Register 1 (T1C1) T1C1 Note: T1RM T1C2 T1C1 T1C0 The three bits T1C[2:0] select the divider for timer 1. The resulting time interval depends on this divider and the timer 1 ...
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Table 6-6. T1C2 6.3.1.2 Timer 1 Control Register 2 (T1C2) T1C2 Note: T1BP T1CS T1IM 6.3.1.3 Watchdog Control Register (WDC) WDC Note: WDL WDR WDT1 WDT0 ATAM894 34 Timer 1 Control Bits ...
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Both these bits control the time interval for the watchdog reset. Table 6-7. WDT1 6.3.2 Timer 2 6.3.2.1 Features 8/12-bit timer for • Interrupt, square-wave, pulse and duty cycle generation • Baud-rate generation for the internal ...
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For programming the time interval, the timer has a 4-bit and an 8-bit compare register. For pro- gramming the timer function, it has four mode and control registers. The comparator output of stage 2 is controlled by a special compare ...
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Timer 2 Modes Mode 1: 12-bit Compare Counter The 4-bit stage and the 8-bit stage work together as a 12-bit compare counter. A compare match signal of the 4-bit and the 8-bit stage generates the signal for the counter ...
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Mode 3/4: 8-bit Compare Counter and 4-bit Programmable Prescaler In these modes the 4-bit and the 8-bit counter stages work independently as a 4-bit prescaler and an 8-bit timer with an 2-bit prescaler duty cycle generator. Only ...
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Timer 2 Output Modes The signal at the timer output is generated via modulator 2. In the toggle mode, the compare match event toggles the output T2O. For high resolution duty cycle modulation 8 bits or 12 bits can ...
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Toggle Mode B: A Timer 2 compare match toggles the output flip-flop (M2) Figure 6-16. Pulse Generator — the Timer Output Toggles with the Timer Start if the T2TS bit Counter 2 Counter 2 Toggle Mode Timer ...
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Timer 2 Output Mode 2 Duty Cycle Burst Generator 1: The DCG output signal (DCGO) is given to the output, and gated by the output flip-flop (M2) Figure 6-18. Carrier Frequency Burst Modulation with Timer 2 Toggle Flip-flop Output Timer ...
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Timer 2 Output Mode 5 Manchester Modulator: Timer 2 Modulates the SSI internal data output (SO) to Manchester code Figure 6-21. Manchester Modulation Timer 2 Output Mode 7 PWM Mode: Pulse-width modulation output on Timer 2 output pin (T2O) In ...
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Timer 2 Registers Timer 2 has 6 control registers to configure the timer mode, the time interval, the input clock and its output function. All registers are indirectly addressed using extended addressing as described in section BP41 or BP42 ...
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Table 6-9. T2D1 Table 6-10. Mode 6.3.2.8 Duty Cycle Generator The duty cycle generator generates duty cycles of 25%, 33% or 50%. The frequency at the duty cycle generator output depends on ...
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Timer 2 Mode Register 2 (T2M2) T2M2 T2TOP T2OS2 T2OS1 T2OS0 Table 6-11. Output Mode one of these output modes is used the T2O alternate function of Port 4 must ...
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Timer 2 Compare Mode Register (T2CM) T2CM T2OTM T2CTM T2RM T2IM Table 6-12. Timer 2 Output Mode 6.3.2.12 Timer 2 COmpare Register 1 (T2CO1) T2CO1 In prescaler mode the clock is bypassed if the compare register T2CO1 contains 0. ...
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Timer 3 6.3.3.1 Features • Two Compare Registers • Capture Register • Edge Sensitive Input with Zero Cross Detection Capability • Trigger and Single Action Modes • Output Control Modes • Automatic Modulation and Demodulation Modes • FSK Modulation ...
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A special feature of this timer is the trigger- and single-action mode. In trigger mode, the counter starts counting triggered by the external signal at its input. In single-action mode, the counter counts only one time up to the programmed ...
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Most of the timer modes use their compare registers alternately. After the start has been acti- vated, the first comparison is carried out via the compare register 1, the second is carried out via the compare register 2, the third ...
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Figure 6-27. Counter Reset with Compare Register 2 and Toggle with Start Figure 6-28. Single Action of Compare Register 1 Counter 3 Timer 3 – Mode 2: The counter is driven by an internal clock source. After starting with T3R, ...
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Timer 3 – Mode 3: The counter is driven by an internal or external (T3I) clock source. The output toggle signal of Timer 2 resets the counter. The counter value before the reset is saved in the capture register. If ...
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Timer 3 – Mode 8: FSK Modulation with Shift Register Data (SO) The two compare registers are used for generating two different time intervals. The SSI internal data output (SO) selects which compare register is used for the output frequency ...
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Timer 3 – Mode 10: Manchester Demodulation/ Pulse-width Demodulation For Manchester demodulation, the edge detection stage must be programmed to detect each edge at the input. These edges are evaluated by the demodulator stage. The timer stage is used to ...
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Timer 3 – Mode 12: Timer/Counter with External Capture Mode (T3I) The counter is driven by an internal clock source and an edge at the external input T3I loads the counter value into the capture register. The edge can be ...
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Timer 3 Demodulator for Bi-phase, Manchester and Pulse-width-modulated Signals The demodulator stage of Timer 3 can be used to decode Bi-phase, Manchester and puls-width-coded signals Figure 6-37. Timer 3 Demodulator 3 6.3.3.6 Timer 3 Registers 6.3.3.7 Timer 3 Mode ...
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Table 6-13. Mode Note: 6.3.3.8 Timer 3 Control Register 1 (T3C) Write Write T3EIM T3TOP T3TS T3R 6.3.3.9 Timer 3 Status Register 1 (T3ST) Read Read T3ED T3C2 T3C1 Note: ATAM894 56 Timer ...
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Timer 3 Clock Select Register (T3CS) T3CS T3E1 T3E0 Table 6-14. T3E1 T3CS1 T3CS0 Table 6-15. 6.3.3.11 Timer 3 Compare- and Compare Mode Register Timer 3 has two separate compare registers T3CO1 and T3CO2 for the 8-bit stage of ...
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Timer 3 Compare Mode Register 1 (T3CM1) T3CM1 T3SM1 T3TM1 T3RM1 T3IM1 T3CM1 contains the mask bits for the match event of the Counter 3 compare register 1 6.3.3.13 Timer 3 Compare Mode Register 2 (T3CM2) T3CM2 T3SM2 T3TM2 ...
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The compare registers and corresponding counter reset masks can be used to program the counter time intervals and the toggle masks can be used to program the output signal. The sin- gle-action mask can also be used in this mode. ...
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Synchronous Serial Interface (SSI) 6.3.4.1 SSI Features • 2- and 3-wire NRZ • 2-wire mode (MCL compatible), additional internal 2-wire link for multi-chip packaging solutions • With Timer 2 – Bi-phase modulation – Manchester modulation – Pulse-width demodulation – ...
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Figure 6-38. Block Diagram of the Synchronous Serial Interface TOG2 POUT T1OUT SYSCL 6.3.4.3 General SSI Operation The SSI is comprised essentially of an 8-bit shift register with two associated 8-bit buffers the receive buffer (SRB) for capturing the incoming ...
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Before data can be transferred, the SSI must first be activated. This is performed by means of the SSI reset control (SIR) bit. All further operation then depends on the data directional mode (TX/RX) and the present status of the ...
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Deactivating the SSI (SIR = 1) in mid-telegram will immediately stop the shift clock and latch the present contents of the shift register into the receive buffer. This can be used for clocking in a data telegram of less than ...
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Shift Mode In the 9-bit shift mode, the SSI is able to handle the MCL protocol (described below). It always operates as an MCL master device, i.e always generated and output by the SSI. Both the ...
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Figure 6-43. Example of MCL Receive Dialog 6.3.4.6 8-bit Pseudo MCL Mode In this mode, the SSI exhibits all the typical MCL operational features except for the acknowl- edge-bit which is never expected or transmitted. 6.3.4.7 MCL Bus Protocol The ...
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Figure 6-44. MCL Bus Protocol Bus not busy (1) Start data transfer (2) Stop data transfer (3) Data valid (4) Acknowledge Figure 6-45. MCL Bus Protocol Start 6.3.4.8 SSI Interrupt The SSI interrupt INT3 ...
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Modulation and Demodulation If the shift register is used together with Timer 2 or Timer 3 for modulation or demodulation pur- poses, the 8-bit synchronous mode must be used. In this case, the unused Port 4 pins can be ...
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Serial Interface Registers 6.3.4.12 Serial Interface Control Register 1 (SIC1) SIC1 SIR SCD SCS1 SCS0 Note: Table 6-16. SCS1 • In transmit mode (SDD = 1) shifting starts only if the transmit buffer has been loaded (SRDY = 1). ...
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Serial Interface Control Register 2 (SIC2) SIC2 MSM SM1 SM0 Table 6-17. Mode SDD Note: 4679D–4BMCU–05/05 Bit 3 Bit 2 MSM SM1 Modular Stop Mode MSM = 1, modulator stop mode disabled (output masking off) MSM = 0, modulator ...
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Serial Interface Status and Control Register (SISC) SISC write SISC read MCL RACK TACK SIM IFN SRDY ACT 6.3.4.15 Serial Transmit Buffer (STB) – Byte Write First write cycle Second write cycle The STB is the transmit buffer of ...
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Serial Receive Buffer (SRB) – Byte Read First read cycle Second read cycle The SRB is the receive buffer of the SSI. The shift register clocks serial data in (most significant bit first) and the loads content into the ...
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Combination Mode 1: Burst Modulation SSI mode 1: Timer 2 mode Timer 2 output mode 3: Figure 6-49. Carrier Frequency Burst Modulation with the SSI Internal Data Output Counter 2 Combination Mode 2: Bi-phase Modulation ...
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Figure 6-51. Manchester Modulation 1 Combination Mode 4: Manchester Modulation 2 SSI mode 1: Timer 2 mode 3: Timer 2 output mode 5: The 4-bit stage can be used as prescaler for the SSI to generate the stop signal for ...
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Combination Mode 5: Bi-phase Modulation 2 SSI mode 1: Timer 2 mode 3: Timer 2 output mode 4: The 4-bit stage can be used as prescaler for the SSI to generate the stop signal for modulator 2. The SSI has ...
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Combination Mode Timer 3 and SSI Figure 6-54. Combination Timer 3 and SSI T3CS T3I T3EX CL3 SYSCL T1OUT POUT RES Compare 3/1 T3CO1 Combination Mode 6: FSK Modulation SSI mode 1: Timer 3 mode 8: The two compare ...
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Figure 6-55. FSK Modulation Counter 3 Combination Mode 7: Pulse-width Modulation (PWM) SSI mode 1: Timer 3 mode 9: The two compare registers are used to generate two varied time intervals. The SSI data output selects which compare register is ...
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Combination Mode 8: Manchester Demodulation/Pulse-width Demodulation SSI mode 1: Timer 3 mode 10: For Manchester demodulation, the edge detection stage must be programmed to detect each edge at the input. These edges are evaluated by the demodulator stage. The timer ...
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Combination Mode 9: Bi-phase Demodulation SSI mode 1: Timer 3 mode 11: In the Bi-phase demodulation mode the timer works like in the Manchester demodulation mode. The difference is that the bits are decoded with the toggle flip-flop. This flip-flop ...
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Combination Mode Timer 2 and Timer 3 Figure 6-59. Combination Timer 3 and Timer 2 T3CS T3I T3EX CL3 SYSCL T1OUT POUT RES Compare 3/1 T3CO1 T2I TOG3 CL2/1 SYSCL T1OUT SCL RES T2C I/O-bus Combination Mode 10: Frequency ...
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Figure 6-60. Frequency Measurement Counter 3 Register Figure 6-61. Event Counter with Time Gate Counter 3 Register Combination Mode 11: Burst Modulation 1 Timer 2 mode 1/2: Timer 2 output mode 1/6: Timer 3 mode 6: The Timer 3 counter ...
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Combination Timer 2, Timer 3 and SSI Figure 6-63. Combination Timer 2, Timer 3 and SSI T3CS T3I T3EX CL3 SYSCL 8-bit Counter 3 T1OUT POUT RES Compare 3/1 T3CO1 T2I TOG3 CL2/1 SYSCL 4-bit Counter 2/1 T1OUT SCL ...
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Combination Mode 12: Burst Modulation 2 SSI mode 1: Timer 2 output mode 2: Timer 2 output mode 1/6: Timer 3 mode 7: The Timer 3 counter is driven by an internal or external clock source. Its compare- and compare ...
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Figure 6-65. FSK Modulation 7. Data EEPROM The internal data EEPROM offers 2 pages of 512 bits each. Both pages are organized bit words. The programming voltage as well as the write cycle timing is generated on ...
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Serial Interface The EEPROM uses an MCL-like two-wire serial interface to the microcontroller for read and write accesses to the data considered slave in all these applications. That means, the controller has to be ...
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Control Byte Format Start Start 7.1.2 EEPROM The EEPROM has a size of 2 and write data to and from the EEPROM the serial interface must be used. The interface sup- ports one and two byte write accesses and ...
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Write One Data Byte Start Write Two Data Bytes Start Write Control Byte Only Start Write Control Bytes Write low byte first Byte order Write high byte first Byte order A acknowledge; HB: high byte; LB: low byte; R: row ...
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Read One Data Byte Start Read Two Data Bytes Start Read n Data Bytes Start Read Control Bytes Read low byte first, address increment Byte order Read high byte first, address decrement Byte order A acknowledge, N 7.1.2.5 Initializing the ...
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Absolute Maximum Ratings Voltages are given relative to V SS. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these ...
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DC Operating Characteristics (Continued 0V –40°C to +85°C unless otherwise specified SS amb Parameters Power-on Reset Threshold Voltage POR threshold voltage POR threshold voltage POR hysteresis Voltage Monitor Threshold Voltage VM high threshold voltage VM ...
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AC Characteristics Supply voltage V = 1.8 to 6.5V Parameters Operation Cycle Time System clock cycle Timer 2 input Timing Pin T2I Timer 2 input clock Timer 2 input LOW time Timer 2 input HIGH time ...
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AC Characteristics (Continued) Supply voltage V = 1.8 to 6.5V Parameters 32-kHz Crystal Oscillator (Operating Range V Frequency Start-up time Stability Integrated input/output capacitances (configurable) External 32-kHz Crystal Parameters Crystal frequency Serial resistance Static capacitance Dynamic ...
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Emulation The basic function of emulation is to test and evaluate the customer's program and hardware in real time. This therefore enables the analysis of any timing, hardware or software problem. For emulation purposes, all MARC4 controllers include a ...
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... Ordering Information (1) Extended Type Number ATAM894x-TNQY ATAM894x-TNSY Note Hardware revision Y = Lead-free 14. Package Information Package SSO24 Dimensions in mm 0.25 0. 4679D–4BMCU–05/05 Program Memory Data-EEPROM 8 kB Flash 2 512 Bit 8 kB Flash 2 512 Bit 8.05 7.80 1.30 0.15 0.05 7. ATAM894 Package Delivery SSO24 Taped and reeled ...
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Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4679D-4BMCU-05/05 4679C-4BMCU-03/04 ATAM894 94 History Put datasheet in a new template Lead-free Logo ...
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Table of Contents Features ..................................................................................................... 1 1 Description ............................................................................................... 1 2 Pin Configuration ..................................................................................... 2 3 Introduction .............................................................................................. 3 4 Differences Between ATAM894 and ATARx90/x92 ............................... 3 5 MARC4 Architecture ................................................................................ 4 6 Peripheral Modules ................................................................................ 22 7 Data ...
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Revision History ..................................................................................... 94 16 Table of Contents.................................................................................... 95 ATAM894 96 4679D–4BMCU–05/05 ...
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 ...