ATAM894X-TNQY ATMEL [ATMEL Corporation], ATAM894X-TNQY Datasheet - Page 57
ATAM894X-TNQY
Manufacturer Part Number
ATAM894X-TNQY
Description
8k-flash Microcontroller
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATAM894X-TNQY.pdf
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6.3.3.10
6.3.3.11
4679D–4BMCU–05/05
Timer 3 Clock Select Register (T3CS)
Timer 3 Compare- and Compare Mode Register
Table 6-14.
Table 6-15.
Timer 3 has two separate compare registers T3CO1 and T3CO2 for the 8-bit stage of Timer 3.
The timer compares the content of the compare register with the current counter value. If both
match, it generates a signal. This signal can be used for the counter reset, to generate a timer
interrupt, for toggling the output flip-flop, as SSI clock or as clock for the next counter stage. For
each compare register, a compare-mode register exists. These registers contain mask bits to
enable or disable the generation of an interrupt, a counter reset, or an output toggling with the
occurrence of a compare match of the corresponding compare register. The mask bits for acti-
vating the single-action mode can also be located in the compare mode registers. When
assigned to the compare register a compare event will be suppressed.
T3CS
T3E1
T3E0
T3CS1
T3CS0
T3E1
T3CS1
1
1
0
0
1
1
0
0
Timer 3 Edge select bit 1
Timer 3 Edge select bit 0
Timer 3 Clock Source select bit 1
Timer 3 Clock Source select bit 0
Timer 3 Edge Select Bits
Timer 3 Clock Select Bits
T3E1
T3E0
Bit 3
1
0
1
0
TCS0
1
0
1
0
Timer 3 Input Edge Select (T3I)
–
Positive edge at T3I pin
Negative edge at T3I pin
Each edge at T3I pin
T3E0
Bit 2
Counter 3 Input Signal (CL3)
System clock (SYSCL)
Output signal of Timer 2 (POUT)
Output signal of Timer 1 (T1OUT)
External input signal from T3I edge detect
T3CS1
Bit 1
T3CS0
Bit 0
Address: 'B'hex — Subaddress: '1'hex
Reset value: 1111b
ATAM894
57
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