EPM2210F100A ALTERA [Altera Corporation], EPM2210F100A Datasheet - Page 82

• Manufacturer Part Number: EPM2210F100A
• Description: MAX II Device Family
• Manufacturer: ALTERA [Altera Corporation]

5–24
Table 5–31. MAX II JTAG Timing Parameters (Part 2 of 2)
Referenced Documents
MAX II Device Handbook
t
t
Notes to
(1) Minimum clock period specified for 10 pF load on the TDO pin. Larger loads on TDO will degrade the maximum TCK
(2) This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For 1.8-V
JSZX
JSXZ
frequency.
LVTTL/LVCMOS and 1.5-V LVCMOS, the t
Symbol
Table
5–31:
Update register high impedance to valid output
Update register valid output to high impedance
This chapter references the following documents:
■
■
■
■
■
■
■
I/O Structure section in the
Handbook
Hot Socketing and Power-On Reset in MAX II Devices
Handbook
Operating Requirements for Altera Devices Data Sheet
PowerPlay Power Analysis
Understanding and Evaluating Power in MAX II Devices
Handbook
Understanding Timing in MAX II Devices
Using MAX II Devices in Multi-Voltage Systems
Handbook
Parameter
JPSU
minimum is 6 ns and t
chapter in volume 3 of the Quartus II Handbook
MAX II Architecture
JPCO
, t
JPZX
, and t
Min
—
—
JPXZ
chapter in the MAX II Device Handbook
are maximum values at 35 ns.
chapter in the MAX II Device
chapter in the MAX II Device
Chapter 5: DC and Switching Characteristics
Max
25
25
chapter in the MAX II Device
chapter in the MAX II Device
© Novermber 2008 Altera Corporation
Unit
ns
ns
Referenced Documents