EPM2210F100A ALTERA [Altera Corporation], EPM2210F100A Datasheet - Page 31

• Manufacturer Part Number: EPM2210F100A
• Description: MAX II Device Family
• Manufacturer: ALTERA [Altera Corporation]

Chapter 2: MAX II Architecture
I/O Structure
I/O Structure
Fast I/O Connection
© October 2008 Altera Corporation
IOEs support many features, including:
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MAX II device IOEs contain a bidirectional I/O buffer.
IOE structure. Registers from adjacent LABs can drive to or be driven from the IOE’s
bidirectional I/O buffers. The Quartus II software automatically attempts to place
registers in the adjacent LAB with fast I/O connection to achieve the fastest possible
clock-to-output and registered output enable timing. For input registers, the
Quartus II software automatically routes the register to guarantee zero hold time.
You can set timing assignments in the Quartus II software to achieve desired I/O
timing.
A dedicated fast I/O connection from the adjacent LAB to the IOEs within an I/O
block provides faster output delays for clock-to-output and t
This connection exists for data output signals, not output enable signals or input
signals.
LVTTL and LVCMOS I/O standards
3.3-V, 32-bit, 66-MHz PCI compliance
Joint Test Action Group (JTAG) boundary-scan test (BST) support
Programmable drive strength control
Weak pull-up resistors during power-up and in system programming
Slew-rate control
Tri-state buffers with individual output enable control
Bus-hold circuitry
Programmable pull-up resistors in user mode
Unique output enable per pin
Open-drain outputs
Schmitt trigger inputs
Fast I/O connection
Programmable input delay
Figure
2–20,
Figure
2–21, and
Figure 2–22
illustrate the fast I/O connection.
Figure 2–19
PD
propagation delays.
shows the MAX II
MAX II Device Handbook
2–23