EPM2210F100A ALTERA [Altera Corporation], EPM2210F100A Datasheet - Page 53

• Manufacturer Part Number: EPM2210F100A
• Description: MAX II Device Family
• Manufacturer: ALTERA [Altera Corporation]

Chapter 4: Hot Socketing and Power-On Reset in MAX II Devices
Hot Socketing Feature Implementation in MAX II Devices
Figure 4–1. Hot Socketing Circuit Block Diagram for MAX II Devices
© October 2008 Altera Corporation
f
1
Make sure that the V
SRAM download has completed.
Each I/O and clock pin has the circuitry shown in
The POR circuit monitors V
until the device has completed its flash memory configuration of the SRAM logic. The
weak pull-up resistor (R) from the I/O pin to V
keep the I/O pins from floating. The 3.3-V tolerance control circuit permits the I/O
pins to be driven by 3.3 V before V
I/O pins from driving out when the device is not fully powered or operational. The
hot socket circuit prevents I/O pins from internally powering V
driven by external signals before the device is powered.
For information about 5.0-V tolerance, refer to the
Voltage Systems
Figure 4–2
This design ensures that the output buffers do not drive when V
V
voltage spikes during hot insertion. The V
tolerant circuit capacitance.
Resistor
Pull-Up
CCINT
Weak
PAD
or if the I/O pad voltage is higher than V
shows a transistor-level cross section of the MAX II device I/O buffers.
chapter in the MAX II Device Handbook.
V
CCINT
CCIO
is within the recommended operating range even though
CCINT
and V
Input Buffer
to Logic Array
CCIO
Tolerance
Voltage
Control
CCIO
and/or V
voltage levels and keeps I/O pins tri-stated
PAD
Output Enable
leakage current charges the 3.3-V
CCIO
CCIO
CCINT
Using MAX II Devices in Multi-
Figure
. This also applies for sudden
is enabled during download to
Hot Socket
are powered, and it prevents the
Power On
Monitor
Reset
4–1.
CCIO
CCIO
is powered before
and V
MAX II Device Handbook
CCINT
when
4–3