PCF2129AT NXP [NXP Semiconductors], PCF2129AT Datasheet - Page 21

• Manufacturer Part Number: PCF2129AT
• Description: Integrated RTC, TCXO and quartz crystal
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF2129A_1
Product data sheet
The setting of the PORO mode requires that POR_OVRD in register Control_1 is set logic
1 and that the signals at the interface pins SDA/CE and SCL are toggled as illustrated in
Figure
Once the override mode is entered, the device is immediately released from the reset
state and the set-up operation can commence.
The PORO mode is cleared by writing logic 0 to POR_OVRD. POR_OVRD must be
logic 1 before a re-entry into the override mode is possible. Setting POR_OVRD logic 0
during normal operation has no effect except to prevent accidental entry into the PORO
mode.
Fig 12. Power-On Reset Override (PORO) sequence, valid for both I
reset override
SDA/CE
12. All timings shown are required minimums.
SCL
power up
8 ms
Rev. 01 — 13 January 2010
minimum 500 ns
Integrated RTC, TCXO and quartz crystal
PCF2129A
2
C-bus and SPI-bus
minimum 2000 ns
© NXP B.V. 2010. All rights reserved.
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