ADF4106 Analog Devices, ADF4106 Datasheet - Page 9

• Manufacturer Part Number: ADF4106
• Description: PLL Frequency Synthesizer
• Manufacturer: Analog Devices

R COUNTER
The 14-bit R counter allows the input reference frequency to
be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383
are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter (N =
BP + A) and produces an output proportional to the phase and
frequency difference between them. Figure 5 is a simplified
schematic. The PFD includes a programmable delay element
which controls the width of the anti-backlash pulse. This pulse
ensures that there is no deadzone in the PFD transfer function
and minimizes phase noise and reference spurs. Two bits in the
Reference Counter Latch, ABP2 and ABP1 control the width of
the pulse. See Table III.
CP OUTPUT
R DIVIDER
N DIVIDER
INPUT STAGE
N DIVIDER
R DIVIDER
FROM RF
HI
HI
MODULUS
CONTROL
D2
D1
N DIVIDER
N = BP + A
CLR1
CLR2
U1
U2
PRESCALER
Q1
Q2
P/P + 1
PROGRAMMABLE
UP
DOWN
ABP2
DELAY
ABP1
LOAD
LOAD
U3
COUNTER
COUNTER
13-BIT B
6-BIT A
CPGND
V
P
CHARGE
PUMP
TO PFD
CP
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4110 family allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the Function
Latch. Table V shows the full truth table. Figure 6 shows the
MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
Digital lock detect is active high. When LDP in the R counter
latch is set to 0, digital lock detect is set high when the phase
error on three consecutive Phase Detector cycles is less than
15 ns. With LDP set to “1,” five consecutive cycles of less than
15 ns are required to set the lock detect. It will stay set high
until a phase error of greater than 25 ns is detected on any sub-
sequent PD cycle.
The N-channel open-drain analog lock detect should be oper-
ated with an external pull-up resistor of 10 k nominal. When
lock has been detected this output will be high with narrow low-
going pulses.
INPUT SHIFT REGISTER
The ADF4110 family digital section includes a 24-bit input shift
register, a 14-bit R counter and a 19-bit N counter, comprising a
6-bit A counter and a 13-bit B counter. Data is clocked into the
24-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destina-
tion latch is determined by the state of the two control bits
(C2, C1) in the shift register. These are the two LSBs, DB1 and
DB0, as shown in the timing diagram of Figure 1. The truth table
for these bits is shown in Table VI. Table I shows a summary
of how the latches are programmed.
Control Bits
C2
0
0
1
1
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
C1
0
1
0
1
Table I. C2, C1 Truth Table
Data Latch
R Counter
N Counter (A and B)
Function Latch (Including Prescaler)
Initialization Latch
MUX
CONTROL
ADF4106
DGND
DV
DD
MUXOUT