ADF4106 Analog Devices, ADF4106 Datasheet - Page 16

• Manufacturer Part Number: ADF4106
• Description: PLL Frequency Synthesizer
• Manufacturer: Analog Devices

ADF4106
THE INITIALIZATION LATCH
When C2, C1 = 1, 1, the Initialization Latch is programmed. This is
essentially the same as the Function Latch (programmed when
C2, C1 = 1, 0).
However, when the Initialization Latch is programmed there is
an additional internal reset pulse applied to the R and AB
counters. This pulse ensures that the AB counter is at load point
when the AB counter data is latched and the device will begin
counting in close phase alignment.
If the Latch is programmed for synchronous power-down (CE
pin is High; PD1 bit is High; PD2 bit is Low), the internal pulse
also triggers this powerdown. The prescaler reference and the
oscillator input buffer are unaffected by the internal reset pulse
and so close phase alignment is maintained when counting resumes.
When the first AB counter data is latched after initialization, the
internal reset pulse is again activated. However, successive AB
counter loads after this will not trigger the internal reset pulse.
DEVICE PROGRAMMING AFTER INITIAL POWER-UP
After initially powering up the device, there are three ways to
program the device.
Initialization Latch Method
• Apply V
• Program the Initialization Latch (“11” in two LSBs of input
• Do a Function Latch load (“10” in two LSBs of the control
• Do an R load (“00” in two LSBs).
• Do an AB load (“01” in two LSBs).
When the Initialization Latch is loaded, the following occurs:
1. The function latch contents are loaded.
2. An internal pulse resets the R, A, B and timeout counters to
3. Latching the first AB counter data after the initialization
CE Pin Method
• Apply V
• Bring CE low to put the device into power-down. This is an
• Program the Function Latch (10).
• Program the R Counter Latch (00).
• Program the AB Counter Latch (01).
• Bring CE high to take the device out of power-down.
The R and AB counters will now resume counting in close
alignment. Note that after CE goes high, a duration of 1 µs may
be required for the prescaler bandgap voltage and oscillator
input buffer bias to reach steady state.
CE can be used to power the device up and down in order to
check for channel activity. The input register does not need to
be reprogrammed each time the device is disabled and enabled
as long as it has been programmed at least once after V
initially applied.
word). Make sure that F1 bit is programmed to “0.”
word), making sure that the F1 bit is programmed to a “0.”
asynchronous power-down in that it happens immediately.
load state conditions and also three-states the charge pump.
Note that the prescaler bandgap reference and the oscillator
input buffer are unaffected by the internal reset pulse, allow-
ing close phase alignment when counting resumes.
word will activate the same internal reset pulse. Successive
AB loads will not trigger the internal reset pulse unless there
is another initialization.
DD
DD
.
.
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was
Counter Reset Method
• Apply V
• Do a Function Latch Load (“10” in two LSBs). As part of
• Do an R Counter Load (“00” in two LSBs).
• Do an AB Counter Load (“01” in two LSBs).
• Do a Function Latch Load (“10” in two LSBs). As part of
This sequence provides the same close alignment as the initial-
ization method. It offers direct control over the internal reset.
Note that counter reset holds the counters at load point and
three-states the charge pump, but does not trigger synchronous
power-down.
APPLICATION SECTION
Local Oscillator for LMDS Base Station Transmitter
Figure 7 shows the ADF4106 being used with a VCO to pro-
duce the LO for an LMDS base station operation in the
5.4 GHz to 5.8 GHz band.
The reference input signal is applied to the circuit at FREF
and, in this case, is terminated in 50 Ω. A typical base station
system would have either a TCXO or an OCXO driving the
Reference Input without any 50 Ω termination.
In order to have a channel spacing of 1 MHz at the output, the
10 MHz reference input must be divided by 10, using the on-chip
reference divider of the ADF4106.
The charge pump output of the ADF4106 (Pin 2) drives the
loop filter. In calculating the loop filter component values, a
number of items need to be considered. In this example, the
loop filter was designed so that the overall phase margin for the
system would be 45 degrees. Other PLL system specifications
are given below:
All of these specifications are needed and used to come up with
the loop filter component values shown in Figure 7.
Figure 7 gives a typical phase noise performance of –83 dBc/Hz
at 1 kHz offset from the carrier. Spurs are better than –62 dBc.
The loop filter output drives the VCO, which, in turn, is fed
back to the RF input of the PLL synthesizer and also drives the
RF Output terminal. A T-circuit configuration provides 50 Ω
matching between the VCO output, the RF output and the
RF
input looks like 50 Ω at 5.8 GHz and so no terminating resistor
is needed. When operating at lower frequencies however, this is
not the case.
In a PLL system, it is important to know when the system is in
lock. In Figure 7, this is accomplished by using the MUXOUT
signal from the synthesizer. The MUXOUT pin can be pro-
grammed to monitor various internal signals in the synthesizer.
One of these is the LD or lock-detect signal.
this, load “1” to the F1 bit. This enables the counter reset.
this, load “0” to the F1 bit. This disables the counter reset.
K
K
Loop Bandwidth = 50 kHz
F
N = 5800
Extra Reference Spur Attenuation = 10 dB
IN
REF
D
V
terminal of the synthesizer. Note that the ADF4106 RF
= 80 MHz/V
= 2.5 mA
= 1 MHz
DD
.
IN