k4t51043qb-gce6 Samsung Semiconductor, Inc., k4t51043qb-gce6 Datasheet - Page 28

• Manufacturer Part Number: k4t51043qb-gce6
• Description: 512mb B-die Ddr2 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

512Mb B-die DDR2 SDRAM
IDD Specification Parameters and Test Conditions
(IDD values are for full operating range of Voltage and Temperature, Notes 1 - 5)
Sym-
bol
IDD0
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
Proposed Conditions
Operating one bank active-precharge current;
CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Operating one bank active-read-precharge current;
IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
t CK = t CK(IDD), t RC = t RC (IDD), t RAS = t RASmin(IDD),
t RCD = t RCD(IDD);
CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
Precharge power-down current;
All banks idle;
t CK = t CK(IDD);
CKE is LOW;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Precharge quiet standby current;
All banks idle;
t CK = t CK(IDD);
CKE is HIGH, CS\ is HIGH;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Precharge standby current;
All banks idle;
t CK = t CK(IDD);
CKE is HIGH, CS\ is HIGH;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active power-down current;
All banks open;
t CK = t CK(IDD);
CKE is LOW;
Other control and address bus inputs are
STABLE;
Data bus inputs are FLOATING
Active standby current;
All banks open;
t CK = t CK(IDD), t RAS = t RASmax(IDD), t RP = t RP(IDD);
CKE is HIGH, CS\ is HIGH between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
t CK = t CK(IDD), t RC = t RC(IDD), t RAS = t RASmin(IDD);
Fast PDN
Exit MRS(12)
= 0mA
Slow PDN
Exit MRS(12)
= 1mA
Page 28 of 38
(CL=5)
DDR2-
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
667
DDR2-
(CL=4)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
533
(CL=3)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
DDR2-
400
Units
mA
mA
mA
mA
mA
mA
mA
mA
Rev. 0.91 (Sep. 2003)
DDR2 SDRAM
Preliminary
Notes