k4t51043qb-gce6 Samsung Semiconductor, Inc., k4t51043qb-gce6 Datasheet - Page 14

• Manufacturer Part Number: k4t51043qb-gce6
• Description: 512mb B-die Ddr2 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

512Mb B-die DDR2 SDRAM
3. Command Truth Table.
(Extended) Mode Register Set
Refresh (REF)
Self Refresh Entry
Self Refresh Exit
Single Bank Precharge
Precharge all Banks
Bank Activate
Write
Write with Auto Precharge
Read
Read with Auto-Precharge
No Operation
Device Deselect
Power Down Entry
Power Down Exit
1. All DDR2 SDRAM commands are defined by states of CS, RAS, CAS , WE and CKE at the rising edge of the clock.
2. Bank addresses BA0, BA1, BA2 (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode
3. Burst reads or writes at BL=4 cannot be terminated or interrupted. See sections "Reads interrupted by a Read" and "Writes inter-
4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. See
6. “X” means “H or L (but a defined logic level)”.
7. Self refresh exit is asynchronous.
3.1 Command truth table.
Register.
rupted by a Write" in section 2.2.4 for details.
requirements outlined in section 2.2.7.
section 2.2.2.4.
Function
Previous
Cycle
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
CKE
Current
Cycle
H
H
H
H
H
H
H
H
H
H
X
X
H
L
L
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CS
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS
X
H
H
H
H
H
H
X
X
H
X
H
L
L
L
L
L
L
CAS
H
H
H
H
H
H
H
L
L
L
X
L
L
L
L
X
X
X
WE
H
H
X
H
H
H
H
H
X
X
H
X
H
L
L
L
L
L
BA0
BA1
BA2
BA
BA
BA
BA
BA
BA
BA
X
X
X
X
X
X
X
X
A15-A11
Column
Column
Column
Column
X
X
X
X
X
X
X
X
X
Row Address
Rev. 0.91 (Sep. 2003)
DDR2 SDRAM
OP Code
A10
X
X
X
H
H
H
X
X
X
X
L
L
L
Preliminary
Column
Column
Column
Column
A9 - A0
X
X
X
X
X
X
X
X
X
Notes
1,2,3,
1,2,3,
1,2,3
1,2,3
1,2
1,7
1,2
1,2
1,4
1,4
1
1
1
1
1