at52br3224 ATMEL Corporation, at52br3224 Datasheet - Page 9

• Manufacturer Part Number: at52br3224
• Description: Single Plane Flash Combined With Sram
• Manufacturer: ATMEL Corporation

AT52BR3224(T)/3228(T)
erase operation has been suspended, the system can then read data or program data to
any other sector within the device. An address is not required during the Erase Suspend
command. During a sector erase suspend, another sector cannot be erased. To resume
the sector erase operation, the system must write the Erase Resume command. The
Erase Resume command is a one-bus cycle command. The device also supports an
erase suspend during a complete chip erase. While the chip erase is suspended, the
user can read from any sector within the memory that is protected. The command
sequence for a chip erase suspend and a sector erase suspend are the same.
PROGRAM SUSPEND/PROGRAM RESUME: The Program Suspend command allows
the system to interrupt a programming operation and then read data from a different
word within the memory. After the Program Suspend command is given, the device
requires a maximum of 20 µs to suspend the programming operation. After the program-
ming operation has been suspended, the system can then read data from any other
word within the device. An address is not required during the program suspend opera-
tion. To resume the programming operation, the system must write the Program
Resume command. The program suspend and resume are one-bus cycle commands.
The command sequence for the erase suspend and program suspend are the same,
and the command sequence for the erase resume and program resume are the same.
PRODUCT IDENTIFICATION: The product identification mode identifies the device and
manufacturer as Atmel. It may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct
programming algorithm for the Atmel product.
For details, see “Operating Modes” on page 20 (for hardware operation) or “Software
Product Identification Entry/Exit” sections on page 27. The manufacturer and device
codes are the same for both modes.
128-BIT PROTECTION REGISTER: The 32-megabit Flash contains a 128-bit register
that can be used for security purposes in system design. The protection register is
divided into two 64-bit blocks. The two blocks are designated as block A and block B.
The data in block A is non-changeable and is programmed at the factory with a unique
number. The data in block B is programmed by the user and can be locked out such that
data in the block cannot be reprogrammed. To program block B in the protection
register, the four-bus cycle Program Protection Register command must be used as
shown in the “Command Definition in Hex” table on page 14. To lock out block B, the
four-bus cycle Lock Protection Register command must be used as shown in the “Com-
mand Definition in Hex” table. Data bit D1 must be zero during the fourth bus cycle. All
other data bits during the fourth bus cycle are don’t cares. To determine whether block B
is locked out, the Product ID Entry command is given followed by a read operation from
address 80H. If data bit D1 is zero, block B is locked. If data bit D1 is one, block B can
be reprogrammed. Please see the “Protection Register Addressing Table” on page 15
for the address locations in the protection register. To read the protection register, the
Product ID Entry command is given followed by a normal read operation from an
address within the protection register. After determining whether block B is protected or
not, or reading the protection register, the Product ID Exit command must be given prior
to performing any other operation.
RDY/BUSY: For the 32-megabit Flash, an open-drain READY/BUSY output pin pro-
vides another method of detecting the end of a program or erase operation. RDY/BUSY
is actively pulled low during the internal program and erase cycles and is released at the
completion of the cycle. The open-drain connection allows for OR-tying of several
devices to the same RDY/BUSY line. Please see “Status Bit Table” on page 13 for more
details.
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