at52br3224 ATMEL Corporation, at52br3224 Datasheet - Page 6

• Manufacturer Part Number: at52br3224
• Description: Single Plane Flash Combined With Sram
• Manufacturer: ATMEL Corporation

Device Operation
READ: The 32-megabit Flash is accessed like an EPROM. When CE and OE are low
and WE is high, the data stored at the memory location determined by the address pins
are asserted on the outputs. The outputs are put in the high impedance state whenever
CE or OE is high. This dual-line control gives designers flexibility in preventing bus
contention.
COMMAND SEQUENCES: When the device is first powered on, it will be reset to the
read or standby mode, depending upon the state of the control line inputs. In order to
perform other device functions, a series of command sequences are entered into the
device. The command sequences are shown in the “Command Definition in Hex” table
on page 14 (I/O8 - I/O15 are don’t care inputs for the command codes). The command
sequences are written by applying a low pulse on the WE or CE input with CE or WE low
(respectively) and OE high. The address is latched on the falling edge of CE or WE,
whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address locations used in the command
sequences are not affected by entering the command sequences.
RESET: A RESET input pin is provided to ease some system applications. When
RESET is at a logic high level, the device is in its standard operating mode. A low level
on the RESET input halts the present device operation and puts the outputs of the
device in a high impedance state. When a high level is reasserted on the RESET pin,
the device returns to the read or standby mode, depending upon the state of the control
inputs.
ERASURE: Before a word can be reprogrammed, it must be erased. The erased state
of memory bits is a logical “1”. The entire device can be erased by using the Chip Erase
command or individual sectors can be erased by using the Sector Erase command.
CHIP ERASE: The entire device can be erased at one time by using the six-byte chip
erase software code. After the chip erase has been initiated, the device will internally
time the erase operation so that no external clocks are required. The maximum time to
erase the chip is t
.
EC
If the sector lockdown has been enabled, the chip erase will not erase the data in the
sector that has been locked out; it will erase only the unprotected sectors. After the chip
erase, the device will return to the read or standby mode.
SECTOR ERASE: As an alternative to a full chip erase, the device is organized into 71
sectors (SA0 - SA70) that can be individually erased. The Sector Erase command is a
six-bus cycle operation. The sector address is latched on the falling WE edge of the
sixth cycle while the 30H data input command is latched on the rising edge of WE. The
sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is
internally controlled; it will automatically time to completion. The maximum time to erase
a sector is t
. When the sector programming lockdown feature is not enabled, the sec-
SEC
tor will erase (from the same Sector Erase command). An attempt to erase a sector that
has been protected will result in the operation terminating in 2 µs.
WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logi-
cal “0”) on a word-by-word basis. Programming is accomplished via the internal device
command register and is a four-bus cycle operation. The device will automatically gen-
erate the required internal program pulses.
Any commands written to the chip during the embedded programming cycle will be
ignored. If a hardware reset happens during programming, the data at the location being
programmed will be corrupted. Please note that a data “0” cannot be programmed back
to a “1”; only erase operations can convert “0”s to “1”s. Programming is completed after
the specified t
cycle time. The Data Polling feature or the Toggle Bit feature may be
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AT52BR3224(T)/3228(T)
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