at52br3224 ATMEL Corporation, at52br3224 Datasheet - Page 11

• Manufacturer Part Number: at52br3224
• Description: Single Plane Flash Combined With Sram
• Manufacturer: ATMEL Corporation

Figure 1. Data Polling Algorithm
(Configuration Register = 00)
Notes:
1682A–10/01
NO
1. VA = Valid address for programming. During a sec-
2. I/O7 should be rechecked even if I/O5 = “1”
Successful, Write
tor erase operation, a valid address is any sector
address within the sector being erased. During
chip erase, a valid address is any non-protected
sector address.
because I/O7 may change simultaneously with
I/O5.
Read I/O7 - I/O0
Read I/O7 - I/O0
Program/Erase
I/O3, I/O5 = 1?
Exit Command
Operation Not
I/O7 = Data?
Product ID
I/O7 = Data?
Addr = VA
Addr = VA
START
NO
YES
NO
YES
YES
Program/Erase
Read Mode
Successful,
Operation
Device in
Figure 2. Data Polling Algorithm
(Configuration Register = 01)
Note:
NO
1. VA = Valid address for programming. During a sec-
AT52BR3224(T)/3228(T)
tor erase operation, a valid address is any sector
address within the sector being erased. During
chip erase, a valid address is any non-protected
sector address.
Successful, Write
Read I/O7 - I/O0
Program/Erase
I/O3, I/O5 = 1?
Operation Not
Exit Command
Product ID
Addr = VA
I/O7 = 1?
START
YES
YES
Write Product ID
Program/Erase
Exit Command
NO
Successful,
Operation
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