ia186es Innovasic Semiconductor Inc., ia186es Datasheet - Page 47

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ia186es

Manufacturer Part Number
ia186es
Description
8-bit/16-bit Microcontrollers
Manufacturer
Innovasic Semiconductor Inc.
Datasheet

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IA186ES/IA188ES
8-Bit/16-Bit Microcontrollers
4.
A functional block diagram of the IA186ES/IA188ES is shown in Figure 7. This microcontroller
consists of the following functional blocks.
4.1
The BIC manages all accesses to external memory and external peripherals. These peripherals
may be mapped either in memory space or I/O space. The BIC supports both multiplexed and
non-multiplexed bus operations. Multiplexed address and data are provided on the AD [15–0]
bus, while a non-multiplexed address is provided on the A [19–0] bus. The A bus provides
address information for the entire bus cycle (t
information only during the first (t
Chapter 6, AC
The BIC provide the capability to dynamically alter the size of the data bus. By programming
the auxiliary control register (AUXCON), a user may easily support external peripherals and
memory devices of both 8- and 16-bit widths without specialized micro-code managing the data
accesses. The AUXCON register contains 3 programmable bits for this purpose: LSIZ, MSIZ,
and IOSIZ. For details regarding the operation of these bits, see
Registers. The IA186ES microcontroller provides two signals to support this functionality, write
high byte (whb_n) and write low byte (wlb_n). The IA188ES microcontroller requires only a
single write byte (wb_n) signal to support its 8-bit data bus.
The BIC also provides support for PSRAM devices. PSRAM is supported in the lower chip
select (lcs_n) area only. In order to support PSRAM, the CSC must be appropriately
programmed. For details regarding this operation, see
Device Architecture
Bus Interface and Control (BIC)
Chip Selects and Control (CSC)
Programmable I/O
Clock and Power Management
DMA
Interrupt Controller
Timers
Asynchronous Serial Ports (2).
Bus Interface and Control
Specifications.
®
1
) phase of the bus cycle. For details regarding bus cycles, see
UNCONTROLLED WHEN PRINTED OR COPIED
1
Page 47 of 154
–t
IA211050902-15
4
), while the AD bus provides address
Section 4.7, Chips
Section 5.1, Control and
Selects.
December 24, 2008
http://www.Innovasic.com
Customer Support:
Data Sheet
1-888-824-4184

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