ia186es Innovasic Semiconductor Inc., ia186es Datasheet - Page 35

• Manufacturer Part Number: ia186es
• Description: 8-bit/16-bit Microcontrollers
• Manufacturer: Innovasic Semiconductor Inc.

IA186ES/IA188ES
8-Bit/16-Bit Microcontrollers
2.2.15 gnd—Ground
Depending on the package, six or seven pins connect the microcontroller to the system ground.
2.2.16 hlda—Bus Hold Acknowledge (synchronous output)
This pin is pulled high to signal the system that the microntroller has relinquished control of the
local bus, in response to a high on the hold signal by an external bus master, after the
microcontroller has completed the current bus cycle. The assertion of hlda is accompanied by
the tristating of den_n, rd_n, wr_n, s2–s0, ad15–ad0, s6, a19–a0, bhe_n, whb_n, wlb_n, and
dr/r_n, followed by the driving high of the chip selects ucs_n, lcs_n, mcs3_n–mcs0_n, pcs6_n–
pcs5_n, and pcs3_n–pcs0_n. The external bus master releases control of the local bus by the
deassertion of hold that in turn induces the microcontroller to deassert the hlda. The
microcontroller may take control of the bus if necessary (to execute a refresh for example), by
deasserting hlda without the bus master first deasserting hold. This requires that the external bus
master must be able to deassert hold to permit the microcontroller to access the bus.
2.2.17 int0—Maskable Interrupt Request 0 (asynchronous input)
The int0 pin provides an indication that an interrupt request has occurred, and provided that int0
is not masked, program execution will continue at the location specified by the INT0 vector in
the interrupt vector table. Although interrupt requests are asynchronous, they are synchronized
internally and may be edge- or level-triggered. To ensure that it is recognized, the assertion of
the interrupt request must be maintained until it is handled.
2.2.18 int1/select_n—Maskable Interrupt Request 1/Slave Select (both are asynchronous
The int1 pin provides an indication that an interrupt request has occurred. Provided that int1 is
not masked, program execution will continue at the location specified by the INT1 vector in the
interrupt vector table. Although interrupt requests are asynchronous, they are synchronized
internally and may be edge- or level-triggered. To ensure that it is recognized, the assertion of
the interrupt request must be maintained until it is handled.
The select_n pin provides an indication to the microcontroller that an interrupt type has been
placed on the address/data bus when the internal Interrupt Control Unit is slaved to an external
interrupt controller. However, before this occurs, the int0 pin must have indicated an interrupt
request has occurred.
inputs)
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IA211050902-15
December 24, 2008
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