ia186es Innovasic Semiconductor Inc., ia186es Datasheet
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Data Sheet ® ® IA211050902-15 UNCONTROLLED WHEN PRINTED OR COPIED Page 1 of 154 Data Sheet December 24, 2008 http://www.Innovasic.com Customer Support: 1-888-824-4184 ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Copyright Published by Innovasic Semiconductor, Inc. 3737 Princeton Drive NE, Suite 130, Albuquerque, NM 87107 AMD, Am186, and Am188 are trademarks of Advanced Micro Devices, Inc. MILES™ trademark of Innovasic Semiconductor, Inc. ® 2008 by Innovasic Semiconductor, Inc. IA211050902-15 UNCONTROLLED WHEN PRINTED OR COPIED ...
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... Latch Enable (synchronous output) .........................................32 2.2.6 ardy—Asynchronous Ready (level-sensitive asynchronous input) ................32 2.2.7 bhe_n/aden_n (IA186ES only)—Bus High Enable (synchronous output with tristate)/Address Enable (input with internal pullup) ..................32 2.2.8 clkouta—Clock Output A (synchronous output) ............................................33 2.2.9 clkoutb—Clock Output B (synchronous output) ............................................33 2.2.10 cts0_n/enrx0_n/pio21—Clear-to-Send 0/Enable-Receive-Request 0 (both are asynchronous inputs) .......................................................................33 2.2.11 den_n/ds_n/pio5— ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 2.2.14 dt/r_n/pio4—Data Transmit or Receive (synchronous output with tristate) ............................................................................................................34 2.2.15 gnd—Ground ..................................................................................................35 2.2.16 hlda—Bus Hold Acknowledge (synchronous output) ....................................35 2.2.17 int0—Maskable Interrupt Request 0 (asynchronous input) ............................35 2.2.18 int1/select_n—Maskable Interrupt Request 1/Slave Select (both are asynchronous inputs) ......................................................................................35 2.2.19 int2/inta0_n/pwd/pio31—Maskable Interrupt Request 2 (asynchronous input)/Interrupt Acknowledge 0 (synchronous output)/Pulse Width Demodulator (Schmitt trigger input) .............................36 2.2.20 int3/inta1_n/irq— ...
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... Mode Request 1 (input with internal pullup) .........................43 2.2.49 uzi_n/pio26—Upper Zero Indicate (synchronous output) ..............................44 —Power Supply (input)..............................................................................44 2.2. 2.2.51 whb_n (IA186ES only)—Write High Byte (synchronous output with tristate) ............................................................................................................44 2.2.52 wlb_n/wb_n—Write Low Byte (IA186ES only) (synchronous output with tristate)/Write Byte (IA188ES only) (synchronous output with tristate) ............................................................................................................44 2.2.53 wr_n— ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 4.13 Midrange-Memory Chip Selects .................................................................................52 4.14 Peripheral Chip Selects ...............................................................................................53 4.15 Refresh Control ...........................................................................................................53 4.16 Interrupt Control ..........................................................................................................53 4.17 Interrupt Types ............................................................................................................54 4.18 Timer Control ..............................................................................................................55 4.19 Watchdog Timer ..........................................................................................................56 4.20 Direct Memory Access ................................................................................................57 4.21 DMA Operation ...........................................................................................................57 4.22 DMA Channel Control Registers ................................................................................58 4.23 DMA Priority ..............................................................................................................59 4.24 Pulse Width Demodulation .........................................................................................59 4.25 Asynchronous Serial Ports ..........................................................................................60 4.26 Programmable I/O .......................................................................................................60 5. Peripheral Architecture .........................................................................................................62 5 ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 5.1.27 PDATA1 (07ah) and PDATA0 (074h) ...........................................................87 5.1.28 PDIR1 (078h) and PDIR0 (072h) ...................................................................89 5.1.29 PMODE1 (076h) and PMODE0 (070h) .........................................................90 5.1.30 T1CON (05eh) and T0CON (056h) ................................................................91 5.1.31 T2CON (066h) ................................................................................................92 5.1.32 T2COMPA (062h), T1COMPB (05ch), T1COMPA (05ah), T0COMPB (054h), and T0COMPA (052h) ...................................................93 5.1.33 T2CNT (060h), T1CNT (058h), and T0CNT (050h) .....................................93 5 ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 7.1.6 Immediate Bytes ...........................................................................................145 7.1.7 Segment Override Prefix ..............................................................................145 7.1.8 Segment Register ..........................................................................................145 7.2 Explanation of Notation Used in Instruction Set Summary Table ............................146 7.2.1 Opcode ..........................................................................................................146 7.2.2 Flags Affected After Instruction ...................................................................147 8. Innovasic/AMD Part Number Cross-Reference Tables......................................................148 9. Errata ...................................................................................................................................150 9.1 Errata Summary .........................................................................................................150 9.2 Errata Detail ..............................................................................................................150 10 ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Figure 1. IA186ES TQFP Package Diagram ................................................................................17 Figure 2. IA188ES TQFP Package Diagram ................................................................................20 Figure 3. TQFP Package Dimensions ...........................................................................................23 Figure 4. IA186ES PQFP Package Diagram ................................................................................24 Figure 5. IA188ES PQFP Package Diagram ................................................................................27 Figure 6. PQFP Package Dimensions ...........................................................................................30 Figure 7. Functional Block Diagram ............................................................................................48 Figure 8. Crystal Configuration ....................................................................................................49 Figure 9. Organization of Clock ...................................................................................................49 Figure 10 ...
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... Table 8. IA188ES PQFP Alphabetic Pin Listing ..........................................................................29 Table 9. Bus Cycle Types for bhe_n and ad0 ...............................................................................32 Table 10. Bus Cycle Types for s2_n, s1_n, and s0_n ...................................................................42 Table 11. IA186ES and IA188ES Absolute Maximum Ratings ...................................................45 Table 12. IA186ES and IA188ES Thermal Characteristics ..........................................................45 Table 13. DC Characteristics Over Commercial Operating Ranges .............................................46 Table 14 ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 41. Serial Port Status Register ............................................................................................83 Table 42. Serial Port Control Registers ........................................................................................84 Table 43. PIO Pin Assignments ....................................................................................................88 Table 44. PDATA 0 ......................................................................................................................89 Table 45. PDATA 1 ......................................................................................................................89 Table 46. PIO Mode and PIO Direction Settings .........................................................................89 Table 47. PDIR0 ...........................................................................................................................90 Table 48. PDIR1 ...........................................................................................................................90 Table 49. PMODE0 ......................................................................................................................90 Table 50. PMODE1 ......................................................................................................................90 Table 51. Timer0 and Timer1 Mode and Control Registers .........................................................91 Table 52 ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 83. PSRAM Refresh Cycle Timing ..................................................................................123 Table 84. Interrupt Acknowledge Cycle Timing ........................................................................125 Table 85. Software Halt Cycle Timing .......................................................................................127 Table 86. Clock Timing ..............................................................................................................129 Table 87. Ready and Peripheral Timing .....................................................................................131 Table 88. Reset and Bus Hold Timing ........................................................................................133 Table 89. Instruction Set Summary ............................................................................................134 Table 90 ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Arial Bold Designates headings, figure captions, and table captions. Blue Designates hyperlinks (PDF copy only). Italics Designates emphasis or caution related to nearby information. Italics is also used to designate variables, refer to related documents, and to differentiate terms from other common words (e.g., ―During refresh cycles, the a and ad busses may not have the same address during the address phase of the ad bus cycle.‖ ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers ACRONYMS AND ABBREVIATIONS AMD BIC CDRAM CSC DA DMA EOI INSERV ISR LMCS MC MDRAM ™ MILES MMCS NMI PCB PIO PLL POR PQFP PSRAM RCU RoHS SFNM SYSCON TQFP UART UMCS WDT ® Advanced Micro Devices Bus Interface and Control ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 1. Introduction The IA186ES/IA188ES is a form, fit, and function replacement for the original Advanced Micro Devices (AMD ) Am186ES/188ES family of microcontrollers. Innovasic produces replacement ™ ICs using its MILES , or Managed IC Lifetime Extension System, cloning technology that produces replacement ICs far more complex than ―emulation‖ while ensuring they are compatible with the original IC ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 2. Packaging, Pin Descriptions, and Physical Dimensions Information on the packages and pin descriptions for the IA186ES and the IA188ES is provided separately. Refer to sections, figures, and tables for information on the device of interest. 2.1 Packages and Pinouts The Innovasic Semiconductor IA186ES and IA188ES microcontroller is available in the ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 2.1.1 IA186ES TQFP Package The pinout for the IA186ES TQFP package is as shown in Figure 1. The corresponding pinout is provided in Tables 1 and 2. ad0 ad8 ad1 ad9 ad2 ad10 ad3 ad11 ad4 ad12 ad5 gnd ad13 ad6 v cc ad14 ad7 ad15 ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 1. IA186ES TQFP Numeric Pin Listing Pin Name 1 ad0 2 ad8 3 ad1 4 ad9 5 ad2 6 ad10 7 ad3 8 ad11 9 ad4 10 ad12 11 ad5 12 gnd 13 ad13 14 ad6 ad14 17 ad7 18 ad15 19 s6/lock_n/clkdiv2/pio29 20 uzi_n/pio26 21 txd1/pio27 22 rxd1/pio28 23 cts0_n/enrx0_n/pio21 24 rxd0/pio23 25 txd0/pio22 26 rts0_n/rtr0_n/pio20 27 bhe_n/aden_n 28 wr_n ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 2. IA186ES TQFP Alphabetic Pin Listing Name Pin a10 52 a11 51 a12 50 a13 49 a14 48 a15 47 a16 46 a17/pio7 45 a18/pio8 43 a19/pio9 42 ad0 1 ad1 3 ad2 5 ad3 7 ad4 9 ad5 11 ad6 14 ad7 17 ad8 ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 2.1.2 IA188ES TQFP Package The pinout for the IA186ES TQFP package is as shown in Figure 2. The corresponding pinout is provided in Tables 3 and 4. ad0 ao8 ad1 ao9 ad2 ao10 ad3 ao11 ad4 ao12 ad5 gnd ao13 ad6 v cc ao14 ad7 ao15 ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 3. IA188ES TQFP Numeric Pin Listing Pin Name 1 ad0 2 ao8 3 ad1 4 ao9 5 ad2 6 ao10 7 ad3 8 ao11 9 ad4 10 ao12 11 ad5 12 gnd 13 ao13 14 ad6 ao14 17 ad7 18 ao15 19 s6/lock_n/clkdiv2/pio29 20 uzi_n/pio26 21 txd1/pio27 22 rxd1/pio28 23 cts0_n/enrx0_n/pio21 24 rxd0/pio23 25 txd0/pio22 26 rts0_n/rtr0_n/pio20 27 rfsh2_n/aden_n 28 wr_n ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 4. IA188ES TQFP Alphabetic Pin Listing Name Pin a10 52 a11 51 a12 50 a13 49 a14 48 a15 47 a16 46 a17/pio7 45 a18/pio8 43 a19/pio9 42 ale 30 ad0 1 ad1 3 ad2 5 ad3 7 ad4 9 ad5 11 ad6 14 ad7 ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 2.1.3 TQFP Physical Dimensions The physical dimensions for the TQFP are as shown in Figure 3. Figure 3. TQFP Package Dimensions ® Legend: Symbol θ θ 1 θ 2 θ 3 Seating Tolerances of Form and Position Plane ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 2.1.4 IA186ES PQFP Package The pinout for the IA186ES PQFP package is as shown in Figure 4. The corresponding pinout is provided in Tables 5 and 6. rxd0/pio23 txd0/pio22 rts0_n/rtr0_n/pio20 bhe_n/aden_n wr_n rd_n ale ardy s2_n s1_n s0_n gnd clkouta clkoutb gnd a19/pio29 ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 5. IA186ES PQFP Numeric Pin Listing Pin Name 1 rxd0/pio23 2 txd0/pio22 3 rts0_n/rtr0_n/pio20 4 bhe_n/aden_n 5 wr_n 6 rd_n 7 ale 8 ardy 9 s2_n 10 s1_n 11 s0_n 12 gnd clkouta 17 clkoutb 18 gnd 19 a19/pio29 20 a18/pio8 a17/pio7 23 a16 24 a15 25 a14 26 a13 27 a12 ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 6. IA186ES PQFP Alphabetic Pin Listing Name Pin a10 29 a11 28 a12 27 a13 26 a14 25 a15 24 a16 23 a17/pio7 22 a18/pio8 20 a19/pio9 19 ad0 78 ad1 80 ad2 82 ad3 84 ad4 86 ad5 88 ad6 91 ad7 94 ad8 ...
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... Figure 5. IA188ES PQFP Package Diagram ® ® IA188ES IA186ES PQFP TQFP IA211050902-15 UNCONTROLLED WHEN PRINTED OR COPIED Page 27 of 154 Data Sheet December 24, 2008 ad1 ao8 ad0 drq0/int5/pio12 drq1/int6/pio13 tmrin0/pio11 tmrout0/pio10 tmrout1/pio1 ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 7. IA188ES PQFP Numeric Pin Listing Pin Name 1 rxd0/pio23 2 txd0/pio22 3 rts0_n/rtr0_n/pio20 4 bhe_n/aden_n 5 wr_n 6 rd_n 7 ale 8 ardy 9 s2_n 10 s1_n 11 s0_n 12 gnd clkouta 17 clkoutb 18 gnd 19 a19/pio29 20 a18/pio8 a17/pio7 23 a16 24 a15 25 a14 26 a13 27 a12 ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 8. IA188ES PQFP Alphabetic Pin Listing Name Pin a10 29 a11 28 a12 27 a13 26 a14 25 a15 24 a16 23 a17/pio7 22 a18/pio8 20 a19/pio9 19 ad0 78 ad1 80 ad2 82 ad3 84 ad4 86 ad5 88 ad6 91 ad7 94 ale ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 2.1.6 PQFP Physical Dimensions The physical dimensions for the PQFP are as shown in Figure 6. Pin 1 Indicator PLATING Detail ―A‖ ® See Detail ―B‖ See Detail ―A‖ Detail ―B‖ Figure 6. PQFP Package Dimensions IA211050902-15 UNCONTROLLED WHEN PRINTED OR COPIED ...
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... These pins are the system’s source of non-multiplexed I/O or memory addresses and occur a half clkouta cycle before the multiplexed address/data bus (ad15–ad0 for the IA186ES or ao15–ao8 and ad7–ad0 for the IA188ES). The address bus is tristated during a bus hold or reset. ...
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... Latch Enable (synchronous output) This signal indicates the presence of an address on the address bus (ad15–ad0 for the IA186ES or ao15–ao8 and ad7–ad0 for the IA188ES), which is guaranteed to be valid on the falling edge of ale. ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers When using the ad bus, DRAM refresh cycles are indicated by bhe_n/aden_n and ad0, both being high. During refresh cycles, the a and ad busses may not have the same address during the address phase of the ad bus cycle. This would necessitate the use of ad0 as a determinant for the refresh cycle, rather than A0 ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers The enrx0_n is the Enable-Receiver-Request for asynchronous serial port 0 when Bit [4] (ENRX0) in the AUXCON register is 1, and Bit [9] (FC) in the SP0CT register is 1, and it enables the asynchronous serial port receiver. 2.2.11 den_n/ds_n/pio5—Data Enable /Data Strobe (both are synchronous outputs with ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 2.2.15 gnd—Ground Depending on the package, six or seven pins connect the microcontroller to the system ground. 2.2.16 hlda—Bus Hold Acknowledge (synchronous output) This pin is pulled high to signal the system that the microntroller has relinquished control of the local bus, in response to a high on the hold signal by an external bus master, after the microcontroller has completed the current bus cycle. The assertion of hlda is accompanied by the tristating of den_n, rd_n, wr_n, s2– ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 2.2.19 int2/inta0_n/pwd/pio31—Maskable Interrupt Request 2 (asynchronous input)/Interrupt Acknowledge 0 (synchronous output)/Pulse Width Demodulator (Schmitt trigger input) The int2 pin provides an indication that an interrupt request has occurred. Provided that int1 is not masked, program execution will continue at the location specified by the int1 vector in the interrupt vector table ...
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... The mcs0_n pin provides an indication that a memory access is in progress to the midrange memory block. The size of the Midrange Memory Block and its base address are programmable. The mcs0_n may be configured for either 16-bit bus width for the IA186ES microcontroller by the Auxiliary Configuration Register (AUXCON Bit [1]) and is held high during bus hold ...
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... The size of the Midrange Memory Block and its base address are programmable. The mcs3_n may be configured for either 16-bit bus width for the IA186ES microcontroller by the Auxiliary Configuration Register (AUXCON Bit [1]) and is held high during bus hold. If mcs0_n has been programmed as the chip select for the whole middle chip select address range, this pin may be used as PIO ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers during both bus hold and reset. These outputs are asserted with the ad address bus over a 256 byte range each. 2.2.28 pcs2_n/cts1_n/enrx1_n/pio18—Peripheral Chip Select 2 (synchronous output)/Clear-to-Send 1 (asynchronous input)/Enable-Receiver-Request 1 (asynchronous input) The pcs2_n signal provides an indication that a memory access is under way for the third region of the peripheral memory block (I/O or memory address space) ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 2.2.30 pcs5_n/A1/pio3—Peripheral Chip Select 5 (synchronous output)/Latched Address Bit [1] (synchronous output) The pcs5_n signal provides an indication that a memory access is under way for the sixth region of the peripheral memory block (I/O or memory address space). The base address of the peripheral memory block is programmable ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 2.2.35 rfsh2_n/aden_n (IA188ES only)—Refresh 2 (synchronous output with tristate)/Address Enable (input with internal pullup) The rfsh2_n indicates that a DRAM refresh cycle is being performed when it is asserted low. However, this is not valid in PSRAM mode where mcs3_n/rfsh_n is used instead. ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 10. Bus Cycle Types for s2_n, s1_n, and s0_n s2_n s1_n s0_n Interrupt acknowledge Read data from I Write data to I Halt Instruction fetch Read data from memory Write data to memory ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers When Pulse Width Demodulation mode is enabled, tmrin0 is driven internally by int2/inta0_n/pwd allowing for the pin to be configured as pio11. 2.2.43 tmrin1/pio0—Timer Input 1 (synchronous edge-sensitive input) This signal may be either a clock or control signal for the internal timer 1. The timer is incremented by the microcontroller after it synchronizes a rising edge of tmrin1. When not used, tmrin1 must be tied high ...
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... These pins supply power (+5V) to the microcontroller. 2.2.51 whb_n (IA186ES only)—Write High Byte (synchronous output with tristate) This pin and wlb_n provide an indication to the system of which bytes of the data bus (upper, lower, or both) are taking part in a write cycle. The whb_n is asserted with ad15–ad8 and is the logical OR of bhe_n and wr_n tristated during reset. 2.2.52 wlb_n/wb_n— ...
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... Emulators require that s6/lock_n/clkdiv2_n and uzi_n be configured as their normal functions (i.e and uzi_n, respectively). Holding bhe_n/aden_n (IA186ES) or rfsh_n/aden_n (IA188ES) low during the rising edge of res_n, s6, and uzi_n will be configured at reset in their normal functions instead of as PIOs. 3. Maximum Ratings, Thermal Characteristics, and DC Parameters ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 13. DC Characteristics Over Commercial Operating Ranges Symbol Parameter Description V Input Low Voltage (Except x1 Clock Input Low Voltage (x1) IL1 V Input High Voltage (Except res_n IH and x1) V Input High Voltage (res_n) IH1 V Clock Input High Voltage (x1) ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 4. Device Architecture A functional block diagram of the IA186ES/IA188ES is shown in Figure 7. This microcontroller consists of the following functional blocks. Bus Interface and Control (BIC) Chip Selects and Control (CSC) Programmable I/O Clock and Power Management DMA Interrupt Controller Timers Asynchronous Serial Ports (2). ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers a[19:0] ad[15:0] Bus Interface ale bhe_n/aden_n and Control wr_n wlb_n whb_n rd_n res_n Peripheral Control and Registers lcs_n/once0_n mcs3_n/rfsh_n ucs_n/once1_n Chip Selects pcs5_n/a1 pcs6_n/a2 and Control mcs2_n–mcs0_n pcs3_n–pcs0_n Programmable pio[31:0] I/O Note: See pin descriptions for pins that share other functions with PIO pins. ...
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... Bits [11–8]). These clock control bits allow one clock output to run at PLL frequency and the other to run at the power-save frequency (see Figure 9). Power-Save x1, x2 PLL Divisor (/2 to /128) ® x1 IA186ES/ IA188ES x2 Crystal Figure 8. Crystal Configuration Processor Internal Clock Mux Drive enable Time Delay Mux 6 ± ...
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... Reset Configuration Register The data on the address/data bus (ad15–ad0 for the IA186ES and ao15–ao8 and ad7–ad0 for the IA188ES) are written into the Reset Configuration Register when reset is low. This data is system-dependent and is held in the Reset Configuration Register after reset is de-asserted. This ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 4.9 Ready- and Wait-State Programming Each of the memory or peripheral chip-select lines can have a ready signal programmed that can be the ardy or srdy signal. The chip-select control registers (UMCS, LMCS, MMCS, PACS, and MPCS) have a single bit that selects if the external ready signal used or not (R2, Bit [2]). ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers wait-state settings must agree with those for any overlapping chip selects as though they had been configured as chip selects. This is true regardless of whether these pins are configured as PIO and enabled (by writing to the MMCS and MPCS registers for the mcs_n chip selects and to the PACS and MPCS registers for the pcs_n chip selects) ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 4.14 Peripheral Chip Selects There are six peripheral chip selects, pcs6_n, pcs5_n, and pcs3_n–pcs0_n, which may be used within a user-defined memory or I/O block. Except for the spaces associated with the ucs_n, lcs_n, and mcs_n chip selects, the base address can be located anywhere within the 1-Mbyte memory-address space or programmed to the 64-Kbyte I/O space. The pcs4_n is not available. None of the pcs_n pins are active at reset. The pcs6_n– ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers With the exception of int0, the seven external maskable interrupt request pins are multifunctional. One function is for direct-interrupt requests. The int6 and int5 are edge- triggered. The int4–int0 may be either level- or edge-triggered. When configured in cascade mode, int1 and int0 interface with an external 82C59A-type interrupt controller ...
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... Not available in slave mode. 4.18 Timer Control The IA186ES and IA188ES have a WDT and three 16-bit programmable timers. Timer0 and timer1 each has an input and output connected to external pins that permits it to count or time events as well as produce variable duty-cycle waveforms or non-repetitive waveforms. These same timers are used to measure the high- and low-pulse widths of the Pulse Width Demodulator on the pwd pin ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers The value stored in a timer’s associated maximum count register determines its maximum count value. Upon reaching it, the timer count register is reset the same clock cycle that this count was attained. The timer count register does not store this maximum value. Both timer0 and timer1 have a primary and a secondary maximum count register that permits each to alternate between two discrete maximum values ...
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... I/O, I/O to memory, memory to memory, or I/O to I/O. DMA channels may be connected to asynchronous serial ports. The IA186ES microcontroller supports the transfer of both bytes and words to and from even or odd addresses. It does not support word transfers to memory that is configured for byte accesses. The IA188ES does not support word transfers at all. Each data transfer will take two bus cycles (a minimum of 8 clock cycles) ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 20-bit Adder/Subtractor Transfer Counter Ch. 1 Destination Address Ch. 1 Source Address Ch. 1 Transfer Counter Ch. 0 Destination Address Ch. 0 Source Address Ch. 0 4.22 DMA Channel Control Registers See Section 5.1.10, D1CON (0dah) and D0CON specify the following: Whether the data destination is in memory or I/O space (Bit [15]) Whether the destination address is incremented, decremented, or unchanged after each transfer (Bits [14– ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Whether DMA transfers cease upon reaching a designated count (Bit [9]) Whether the last transfer generates an interrupt (Bit [8]) Synchronization mode (Bits [7–6]) The relative priority of one DMA channel with respect to the other (Bit [5]) Acceptance of DMA requests from Timer2 (Bit [4]) ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers The current count of timer1 for INT2 and timer0 for INT4 should be inspected by the ISR to determine the pulse width. The timer count register should then be reset by the ISR in readiness for the next pulse. The timer count rate (one-fourth of the processor clock rate) determines the maximum resolution of the timers ...
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... Emulators use these pins and also s2_n–s0_n, res_n, nmi, clkouta, bhe_n, ale, ad15–ad0, and a16–a0 bhe_n/aden_n (IA186ES) or rfsh_n/aden_n (IA188ES) is held low during POR, these pins will revert to normal operation. d Input with pulldown option available when used as PIO. ...
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... Normal function is also the default setting for dt/r_n, den_n, and srdy after POR. If the ad15–ad0 bus override is enabled, s6/clkdiv2_n and uzi_n automatically return to normal operation. The ad15–ad0 bus override is enabled if either the bhe_n/aden_n for the IA186ES or the rfsh2_n/aden_n for the IA188ES is held low during POR. ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 16. Peripheral Control Registers Register Name Peripheral Control Block Registers PCB Relocation Register Reset Configuration Register Processor Release Level Register Auxiliary Configuration Register System Configuration Register Watchdog Timer Control Register Enable RCU Register Clock Prescaler Register Memory Partition Register ...
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... RC [15–0] Bits [15–0]—RC [15–0] → At the rising edge of reset, the values of specified pins (ad15–ad0 for the IA186ES and ao15–ao8 and ad7–ad0 for the IA188ES) are latched into this register. 5.1.3 PRL (0f4h) The Processor Release Level Register contains a code corresponding to the latest processor production release. The PRL is a read-only register. The PRL contains 1100h (see Table 19). ® ...
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... Bit [3]—RTS0 → When set to 1, the rtr0_n/rts0_n pin functions as rts0_n. When 0, it functions as rtr0_n. Bit [2]—LSIZ (IA186ES only) → When set to 1, 8-bit data accesses are performed in lower chip-select (lcs_n) space. When 0, 16-bit data accesses are performed. ® ...
Page 66
... When 0, 16-bit data accesses are performed. Bit [0]—IOSIZ (IA186ES only) → When set to 1, 8-bit data accesses are performed in all I/O space. When 0, 16-bit data accesses are performed. ...
Page 67
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Bit [8]—CAD → When set to 1, the clkouta output is driven low. When driven as an output per the CBF bit. Bits [7–3]—Reserved → The bits read back as zeros. Bits [2–0]—F2–F0 → These bits control the clock divider as shown below. ...
Page 68
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Bits [10–8]—Reserved. Bits [7–0]—COUNT → Control the timeout period for the WDT as follows: Where The WDT timeout period in seconds. timeout frequency = The processor frequency in hertz. exponent = Is based upon count as shown below: Bit [7] Bit [6] Bit [ ...
Page 69
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 5.1.8 CDRAM (0e2h) The Count for Dynamic RAM (CDRAM) Refresh Control Register determines the period between refresh cycles. The CDRAM register is undefined at reset (see Table 24). Table 24. Count for Dynamic RAM Refresh Control Register Bits [15– ...
Page 70
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Bit [15]—DM/IOn → Destination Address Space Select selects memory or I/O space for the destination address. When DM/IO is set to 1, the destination address is in memory space. When I/O space. Bit [14]—DDEC → Destination Decrement when set to 1, automatically decrements the destination address after each transfer ...
Page 71
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Synchronization Bit Channel Selection SYN1 SYN0 0 0 Unsynchronized 0 1 Source Synchronized 1 0 Destination Synchronized 1 1 Reserved Bit [5]—P → Relative Priority. When set to 1, selects high priority for this channel relative to the other channel during simultaneous transfers. ...
Page 72
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Bits [15–0]—TC [15–0] → DMA Transfer Count contains the transfer count for the respective DMA channel. Its value is decremented after each transfer. 5.1.12 D1DSTH (0d6h) and D0DSTH (0c6h) The DMA DeSTination Address High Register. The 20-bit destination address consists of these 4 bits combined with the 16 bits of the respective Destination Address Low Register ...
Page 73
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers all four address registers be initialized. Each address may be independently incremented or decremented after each word transfer for byte transfers. They are undefined at reset (see Table 30). Table 30. DMA Source Address High Register Reserved Bits [15–4]—Reserved. ...
Page 74
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 32. MCS and PCS Auxiliary Register M6–M0 Bit [15]—Reserved → Set to 1. Bits [14–8]—M [6–0] mcs_n Block Size → These seven bits determine the total memory block size for the mcs3_n–mcs0_n chip selects. The size is divided equally among them. ...
Page 75
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 5.1.17 MMCS (0a6h) Midrange Memory Chip Select (MMCS) Register. Four chip-select pins, mcs3_n–mcs0_n, are provided for use within a user-locatable memory block. Excluding the areas associated with the ucs_n and lcs_n chip selects (and if mapped to memory, the address range of the peripheral chip selects, pcs6_n– ...
Page 76
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Bits [1–0]—R [1–0] → Wait-State Value. The value of these bits determines the number of wait states inserted in an access three wait states can be inserted (R1–R0 = 00b to 11b). 5.1.18 PACS (0a4h) PeripherAl Chip Select Register. These Peripheral Chip Selects are asserted over 256-byte range with the same timing as the ad address bus. There are six chip selects, pcs6_n– ...
Page 77
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Address Ranges of pcs Chip Selects pcs_n Line pcs0_n Base Address pcs1_n Base Address + 256 pcs2_n Base Address + 512 pcs3_n Base Address + 768 Reserved pcs5_n Base Address + 1280 pcs6_n Base Address + 1536 Bits [6–4]—Reserved. Set to 1. Bit [3]—R [3] → Wait State Value. See pcs3_n–pcs0_n Wait-State Encoding shown below. pcs3_n– ...
Page 78
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers The width of the data bus for the lcs_n space should be configured in the AUXCON register before activating the lcs_n chip select pin, by any write access to the LMCS register. The value of the LMCS register is undefined at reset except DA, which is set to 0 (see Table 35). ...
Page 79
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Bits [R1–R0]—R [1–0] → Wait-State Value. The value of these bits determines the number of wait states inserted into an access to the lcs_n memory area. This number ranges from (R1–R0 = 00b to 11b). 5.1.20 UMCS (0a0h) The Upper Memory Chip Select Register configures the UMCS pin, used for the top of memory. ...
Page 80
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Bit [5–3]—Reserved. Set to 1. Bit [2]—R2 Ready Mode → When set to 1, the external ready is ignored. When 0, an external ready is required. The value of these bits determines the number of wait states inserted. Bits [1–0]—R [1–0] Wait-State Value → The value of these bits determines the number of wait states inserted into an access to the lcs_n memory area. This number ranges from (R1– ...
Page 81
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 37. Baud Rates Divisor Based on CPU Clock Rate Baud Rate 20 MHz 25 MHz 300 4166 5208 600 2083 2604 1050 1190 1488 1200 1041 1302 1800 694 868 2400 520 651 4800 260 325 7200 173 217 9600 ...
Page 82
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers If handshaking is employed, the control signals cts_n/enrx_n are deasserted while the receive register has valid unread data. The cts_n/enrx_n signal is reasserted after the data in the receive register is read. The value of the SP0RD and SP1RD registers is undefined at reset (see Table 39) ...
Page 83
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 41. Serial Port Status Register Reserved BRK1 BRK0 RB8 RDR THRE FER OER PER TEMT HS0 Res Bits [15–11]—Reserved. Bit [10]—BRK1 Long Break Detected → A long break is a low signal level on the rxd ...
Page 84
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Bit [6]—THRE Transmit Holding Register Empty → When this bit indicates that the corresponding transmit holding register is ready to accept data. This is a read-only bit. Bit [5]—FER Framing Error Detected → When the receiver samples the rxd line as low when a stop bit is expected (line high), a framing error is generated setting this bit ...
Page 85
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers DMA Control Bits DMA Bits Receive 000b No DMA 001b DMA0 010b DMA1 011b Reserved 100b DMA0 101b DMA1 110b No DMA 111b No DMA – DMA transfers to both serial ports are destination-synchronized operations. When the transmit holding register is empty, a new transfer is requested, corresponding with the assertion of the THRE bit in the status register in non-DMA mode ...
Page 86
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Bit [10]—TB8 Transmit Bit 8 → This is the ninth data bit transmitted when in modes 2 and 3. This bit is cleared at each transmitted word and is not buffered. To transmit data with this bit set high, the following procedure is recommended. 1. The TEMT bit in the serial port status register must go high. ...
Page 87
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Serial Port MODE Settings MODE Description a Data Mode Data Mode 1 2 Data Mode 2 3 Data Mode 3 4 Data Mode 4 a Data Mode Data Mode Data Mode These were originally reserved modes that have been implemented to provide 2 stop bits. – ...
Page 88
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers as an input, the value on the pin is put into the corresponding bit of the PIO data register. Table 43 lists the default states for the PIO pins. Table 43. PIO Pin Assignments PIO Number Associated Pin Name 0 tmrin1 1 tmrout1 2 pcs6/A2 3 pcs5/A1 ...
Page 89
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers The 32 PIO pins initialize to either 00b or 01b as shown in Tables 44 and 45. The value of the PDATA registers is undefined at reset. Table 44. PDATA PDATA (15–0) Table 45. PDATA PDATA (31–16) Bits [15–0]—PDATA [15–0] PIO Data 0 Bits → This register contains the values of the bits that are either driven on, or received from, the corresponding PIO pins ...
Page 90
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers The value of the PDIR0 register is FC0Fh at reset (see Table 48). Table 47. PDIR0 PDIR (15–0) The value of the PDIR1 register is FFFFh at reset (see Table 48). Table 48. PDIR1 PDIR (31–16) Bits [15–0]—PDIR [15–0] PIO Direction 0 Bits → For each bit, if the value is 1, the pin is configured as an input ...
Page 91
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Bits [15–0]—PMODE [31–16] PIO Mode 1 Bits → For each bit, if the value is 1, the pin is configured as an input output. The values of these bits correspond to those in the PIO data registers and PIO Mode registers. 5.1.30 T1CON (05eh) and T0CON (056h) Timer0 and Timer1 Mode and CONtrol Registers ...
Page 92
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Bit [3]—P Prescaler Bit → ignored if external clocking is enabled (EXT = 1). Timer 2 prescales the timer when P is set to 1. Otherwise, the timer is incremented on every fourth CLKOUT cycle. Bit [2]—EXT External Clock Bit → This bit determines whether an external or internal clock is used. If EXT = 1, an external clock is used. If EXT = 0, an internal is used. Bit [1]— ...
Page 93
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Bit [5]—MC Maximum Count → When the timer reaches its maximum count, this bit is set to 1 regardless of the interrupt enable bit. This bit may be used by software polling to monitor timer status rather than through interrupts if desired. Bits [4–1]—Reserved. Set to 0. ...
Page 94
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Comparisons are made between the count registers and maxcount registers and action taken dependent on achieving the maximum count. The value of these registers is 0000h at reset (see Table 54). Table 54. Timer Count Registers TC15–TC0 Bits [15–0]—TC [15–0] Timer Count Value → This register has the value of the current count of the related timer that is incremented every fourth processor clock in internal clocked mode ...
Page 95
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Values of PR2–PR0 by Priority Priority PR2–PR0 (High) 0 000b 1 001b 2 010b 3 011b 4 100b 5 101b 6 110b (Low) 7 111b 5.1.35 I4CON (040h) (Master Mode) INT4 CONtrol Register. The int4 signal is intended only for use in fully nested mode and is not available in cascade mode. The value of the I4CON register is 000Fh at reset (see Table 56). ...
Page 96
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 57. INT2/INT3 Control Register Reserved Bits [15–5]—Reserved. Set to 0. Bit [4]—LTM Level-Triggered Mode → The int2 or int3 interrupt may be edge- or level- triggered depending on the value of this bit. If LTM is 1, int2 or int3 is an active high level-sensitive interrupt ...
Page 97
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers level-sensitive interrupt rising-edge triggered interrupt. The interrupt int0 or int1 must remain active (high) until acknowledged. Bit [3]—MSK Mask → The int0 or int1 signal can cause an interrupt if the MSK bit is 0. The int0 or int1 signal cannot cause an interrupt if the MSK bit is 1. The Interrupt Mask Register has a duplicate of this bit. Bit [2– ...
Page 98
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Bits [15–4]—Reserved. Set to 0. Bit [3]—MSK Mask → Any of the interrupt sources may cause an interrupt if the MSK bit is 0. The interrupt sources cannot cause an interrupt if the MSK bit is 1. The Interrupt Mask Register has a duplicate of this bit. ...
Page 99
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Bits [15–4]—Reserved. Set to 0. Bit [3]—MSK Mask → Any of the interrupt sources may cause an interrupt if the MSK bit is 0. The interrupt sources cannot cause an interrupt if the MSK bit is 1. The Interrupt Mask Register has a duplicate of this bit. ...
Page 100
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Bit [15]—DHLT DMA Halt → DMA activity is halted when this bit set to 1 automatically when any non-maskable interrupt occurs and is cleared to 0 when an IRET instruction is executed. Interrupt handlers and other time critical software may modify this bit directly to disable DMA transfers ...
Page 101
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Bit [1]—Reserved. Bit [0]—TMR Timer Interrupt Request → This is the timer interrupt state and is the logical OR of the timer interrupt requests. When set indicates that the timer control unit has a pending interrupt. 5.1.45 REQST (02eh) (Slave Mode) This read-only register results in the status of interrupt request bits being presented to the interrupt controller ...
Page 102
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 67. In-Service Register (Master Mode Reserved SP0 Bits [15–11]—Reserved. Bit [10]—SP0 Serial Port 0 Interrupt Request → This is the Serial Port 0 interrupt state. Bit [9]—SP1 Serial Port 1 Interrupt Request → This is the Serial Port 1 interrupt state. ...
Page 103
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Bit [4]—TMR1 Timer1 Interrupt IN Service → Timer1 is being serviced when this bit is set to 1. Bit [3]—D1/I6 DMA Channel Interrupt 6 In Service → DMA channel 1 or int6 is being serviced when this bit is set to 1. Bit [2]—D0/I5 DMA Channel Interrupt 5 IN Service → DMA channel 0 or int5 is being serviced when this bit is set to 1. Bit [1]— ...
Page 104
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 70. Interrupt MASK Register (Master Mode Reserved SP0 Bits [15–11]—Reserved. Bit [10]—SP0 Serial Port 0 Interrupt Mask → Setting this bit indication that the serial port 0 interrupt is masked. Bit [9]—SP1 Serial Port 1 Interrupt Mask → Setting this bit indication that the serial port 0 interrupt is masked. Bits [8– ...
Page 105
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Bit [4]—TMR1 Timer1 Interrupt Mask → This bit provides the state of the mask bit in the Timer Interrupt Control register. When set indicates that the interrupt request is masked. Bit [3]—D1/I6 DMA Channel Interrupt 6 Mask → This bit provides the state of the mask bit in the DMA channel 0 or int5 Interrupt Control register ...
Page 106
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 73. Poll Register IREQ Reserved Bit [15]—IREQ Interrupt Request → This bit is set to 1 when an interrupt is pending and during this state, the S4–S0 bits contain valid data. Bits [14–6]—Reserved. Bit [4–0]—S [4–0] Poll Status → These bits show the interrupt type of the highest priority pending interrupt ...
Page 107
... Bits [2–0]—Reserved. Read as 0. 5.2 Reference Documents Additional information on the operation and programming of the IA186ES/ IA188ES can be found in the following AMD publications: Am186 ES and Am188 ES User’s Manual (Publication 21096). Am186 ES/ESLV and Am188 ES/ESLV Preliminary Data Sheet (Publication 20002). ...
Page 108
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 6. AC Specifications Table 77 and Table 78 present the alphabetic and numeric keys to waveform parameters, respectively. Figure 12 presents the read cycle. Table 79 presents the read cycle timing. the write cycle timing. Figure 15 Figure 16 presents the PSRAM read cycle. Figure 17 presents the PSRAM write cycle ...
Page 109
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 77. Alphabetic Key to Waveform Parameters (Continued) No. Name 8 tCHDX Status Hold Time 9 tCHLH ale Active Delay 11 tCHLL ale Inactive Delay 79 tCHRFD clkouta High to rfsh_n Valid 3 tCHSV Status Active Delay 69 tCICOA x1 to clkouta Skew 70 tCICOB x1 to clkoutb Skew 39 tCKHL ...
Page 110
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 77. Alphabetic Key to Waveform Parameters (Continued) No. Name 1 tDVCL Data in Setup 19 tDXDL den_n Inactive to dt/r_n Low 58 tHVCL hld Setup Time 53 tINVCH Peripheral Setup Time 54 tINVCL drq Setup Time 86 tLCRF lcs_n Inactive to rfsh_n Active Delay 23 tLHAV ale High to Address Valid ...
Page 111
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 78. Numeric Key to Waveform Parameters (Continued) No. Name 14 tAVCH ad Address Valid to Clock High 15 tCLAZ ad Address Float Delay 16 tCLCSV mcs_n/pcs_n Inactive Delay 17 tCXCSX mcs_n/pcs_n Hold from Command Inactive 18 tCHCSX mcs_n/pcs_n Inactive Delay 19 tDXDL den_n Inactive to dt/r_n Low 20 tCVCTV Control Active Delay 1 ...
Page 112
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 78. Numeric Key to Waveform Parameters (Continued) No. Name 52 tARYLCL ardy Setup Time 53 tINVCH Peripheral Setup Time 54 tINVCL drq Setup Time 55 tCLTMV Timer Output Delay 57 tRESIN res_n Setup Time 58 tHVCL hld Setup Time 59 tRHDX rd_n High to Data Hold on ad Bus ...
Page 113
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers clkouta a19–a0 s6/lock_n ad15–ad0 (IA186ES), ad7–ad0 (IA188ES) ao15–ao8 (IA188ES) ale rd_n bhe_n (IA186ES) lcs_n, ucs_n mcs_n, pcs_n den_n/ds_n dt/r_n s2_n–s0_n uzi_n ® Figure 12. Read Cycle IA211050902-15 UNCONTROLLED WHEN PRINTED OR COPIED Page 113 of 154 ...
Page 114
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers clkouta a19–a0 ad15–ad0 (IA186ES), ao15–ao8 (IA188ES) ale rd_n lcs_n, ucs_n mcs_n, pcs_n s2_n–s0_n ® Figure 13. Multiple Read Cycles IA211050902-15 UNCONTROLLED WHEN PRINTED OR COPIED Page 114 of 154 Data Sheet December 24, 2008 http://www.Innovasic.com Customer Support: ...
Page 115
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 79. Read Cycle Timing No. Name General Timing Requirements 1 tDVCL Data in Setup 2 tCLDX Data in Hold General Timing Responses 3 tCHSV Status Active Delay 4 tCLSH Status Inactive Delay 5 tCLAV ad Address Valid Delay 6 tCLAX Address Hold 8 tCHDX Status Hold Time 9 tCHLH ...
Page 116
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers clkouta a19–a0 s6/lock_n ad15–ad0 (IA186ES), ad7–ad0 (IA188ES) ao15–ao8 (IA188ES) ale wr_n whb_n, wlb_n (IA186ES), wb_n (IA188ES) bhe_n (IA186ES) lcs_n, ucs_n mcs_n, pcs_n den_n/ds_n dt/r_n s2_n–s0_n uzi_n ® Figure 14. Write Cycle IA211050902-15 UNCONTROLLED WHEN PRINTED OR COPIED ...
Page 117
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers clkouta a19–a0 ad15–ad0 (IA186ES), ao15–ao8 (IA188ES) ale rd_n lcs_n, ucs_n mcs_n, pcs_n s2_n–s0_n ® Figure 15. Multiple Write Cycles IA211050902-15 UNCONTROLLED WHEN PRINTED OR COPIED Page 117 of 154 Data Sheet December 24, 2008 http://www.Innovasic.com Customer Support: ...
Page 118
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 80. Write Cycle Timing No. Name General Timing Requirements 1 tDVCL Data in Setup 2 tCLDX Data in Hold General Timing Responses 3 tCHSV Status Active Delay 4 tCLSH Status Inactive Delay 5 tCLAV ad Address Valid Delay 6 tCLAX Address Hold 8 tCHDX Status Hold Time 9 tCHLH ...
Page 119
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 0ns 20ns clkouta a19–a0 s6/lock_n s6 ad15–ad0 (IA186ES), ad7–ad0 (IA188ES) ao15–ao8 (IA188ES ale rd_n lcs_n n ® 40ns 60ns 80ns 66 Address Address 68 lock_n 5 7 Address 23 Address Address Figure 16. PSRAM Read Cycle ...
Page 120
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 81. PSRAM Read Cycle Timing No. Name General Timing Requirements 1 tDVCL Data in Setup 2 tCLDX Data in Hold General Timing Responses ad Address Valid Delay 5 tCLAV 6 tCLAX Address Hold 8 tCHDX Status Hold Time 9 tCHLH ale Active Delay 10 tLHLL ale Width 11 tCHLL ...
Page 121
... Address Address 68 lock_n 5 7 Address Address ...
Page 122
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 82. PSRAM Write Cycle Timing No. Name General Timing Requirements 1 tDVCL Data in Setup 2 tCLDX Data in Hold General Timing Responses ad Address Valid Delay 5 tCLAV 7 tCLDV Data Valid Delay 8 tCHDX Status Hold Time 9 tCHLH ale Active Delay 10 tLHLL ale Width ...
Page 123
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 0ns 20ns 40ns clk0 a19–a0 9 ale rd_n lcs_n rfsh_n 86 Table 83. PSRAM Refresh Cycle Timing No. Name General Timing Requirements 1 tDVCL Data in Setup 2 tCLDX Data in Hold General Timing Responses ...
Page 124
... CLK0 clk0 a19-a0 a19–a0 s6/lock_n s6/lock_n s6 ad15–ad0 (IA186ES), ad15-ad0/ad7-ad0 ad7–ad0 (IA188ES) ao15-ao8 ao15–ao8 (IA188ES) ale ale bhe_n bhe_n (IA186ES) inta1_n/inta0_n inta1_n, inta0_n den_n den_n dt_r_n dt/r_n s2_n-s0_n s1_n–s0_n Figure 19. Interrupt Acknowledge Cycle ® 40ns 60ns 80ns 68 ...
Page 125
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 84. Interrupt Acknowledge Cycle Timing No. Name General Timing Requirements 1 tDVCL Data in Setup 2 tCLDX Data in Hold General Timing Responses 3 tCHSV Status Active Delay 4 tCLSH Status Inactive Delay 5 tCLAV ad Address Valid Delay 9 tCHLH ale Active Delay 10 tLHLL ale Width ...
Page 126
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 0ns 20ns A clkouta a19– ad15–ad0 (IA186ES), ad8–ad0 (IA188ES), ao15–ao8 (IA188ES) ale den_n dt/r_n _ n s1_n–s0_n ® 40ns 60ns 80ns 68 Invalid Address Invalid Address 5 Invalid Address Invalid Address 9 11 ...
Page 127
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 85. Software Halt Cycle Timing No. Name General Timing Responses 3 tCHSV Status Active Delay 4 tCLSH Status Inactive Delay 7 tCLDV Data Valid Delay 8 tCHDX Status Hold Time 9 tCHLH ale Active Delay 10 tLHLL ale Width 11 tCHLL ale Inactive Delay ad Address Valid to ale Low ...
Page 128
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 0ns 20ns 40ns clkouta clkoutb 0ns 20ns clkouta clkoutb (CBF= clkoutb (CBF=0) ® 60ns 80ns 100ns Figure 21. Clock—Active Mode 40ns 60ns 80ns 100ns Figure 22. Clock—Power-Save Mode ...
Page 129
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 86. Clock Timing No. Name clkin Requirements 36 tCKIN x1 Period 37 tCLCK x1 Low Time 38 tCHCK x1 High Time 39 tCKHL x1 Fall Time 40 tCKLH x1 Rise time clkout Requirements 42 tCLCL clkouta Period 43 tCLCH clkouta Low Time 44 tCHCL clkouta High Time 45 tCH1CH2 clkouta Rise Time ...
Page 130
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 0ns clkouta ardy Sytem Normally not Ready Sytem Normally Ready ardy ardy Figure 24. ardy—Asynchronous Ready 0ns 20ns clkouta int4–int0, nmi tmrin1–tmrin0 drq1–drq0 tmrout1–tmrout0 ® ...
Page 131
... A clkouta rfsh_n/aden_n s6, uzi_n ad15–ad0 (IA186ES), ao15–ao8 (IA188ES), ad7–ad0 (IA188ES) ® Description 60ns 80ns 100ns 57 Low for N x1 Cycles Figure 26. Reset 1 40ns 60ns 80ns ...
Page 132
... Figure 28. Bus Hold Entering 20ns 40ns ...
Page 133
... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 88. Reset and Bus Hold Timing No. Name Reset and Bus Hold Timing Requirements 5 tCLAV ad Address Valid Delay 15 tCLAZ ad Address Float Delay 57 tRESIN res_n Setup Time 58 tHVCL hld Setup Time Reset and Bus Hold Timing Responses 62 tCLHAV hlda Valid Delay ...
Page 134
... CLD Clear direction flag CLI Clear interrupt-enable flag CMC Complement carry flag Refer to the key for abbreviations and an explanation of notation ® Opcode – Hex Clock Cycles Byte Byte 1 Byte 2 3–6 IA186ES IA188ES 37 – – – – – ...
Page 135
... HLT Suspend instruction execution IDIV Divide Integers AL = AX/(r/m8 remainder Divide Integers AX = DX:AX/(r/m16 remainder Refer to the key for abbreviations and an explanation of notation ® Opcode – Hex Clock Cycles Byte Byte 1 Byte 2 3–6 IA186ES IA188ES 3C ib – – 3/10 3/ 3/10 3/14 ...
Page 136
... Jump short if below or equal (C & JNA Jump short if not above (C & Refer to the key for abbreviations and an explanation of notation ® Opcode – Hex Clock Cycles Byte Byte 1 Byte 2 3–6 IA186ES IA188ES F6 /5 – 25–28 25–28 / 31–34 31– – 34–37 34–37 / 40– ...
Page 137
... Decrement count; jump short and LOOPNZ Decrement count; jump short and Refer to the key for abbreviations and an explanation of notation ® Opcode – Hex Clock Cycles Byte Byte 1 Byte 2 3–6 IA186ES IA188ES E3 cb – 15,5 15 – 13 – 13, 4 ...
Page 138
... Output word DS:[SI] to port in DX OUTSB Output byte DS:[SI] to port in DX OUTSW Output word DS:[SI] to port in DX Refer to the key for abbreviations and an explanation of notation ® Opcode – Hex Clock Cycles Byte Byte 1 Byte 2 3–6 IA186ES IA188ES 88 /r – 2/12 2/ – 2/12 2/ – 2/9 ...
Page 139
... Load CX bytes from segment:[SI] LODS in AL Load CX words from segment:[SI Refer to the key for abbreviations and an explanation of notation ® Opcode – Hex Clock Cycles Byte Byte 1 Byte 2 3–6 IA186ES IA188ES 8F /0 – 58+rw – – – – – ...
Page 140
... Rotate 16 bits of r/m8 left once ROL Rotate 16 bits or r/m8 left CL times Rotate 16 bits or r/m8 left imm8 times Refer to the key for abbreviations and an explanation of notation ® Opcode – Hex Clock Cycles Byte Byte 1 Byte 2 3–6 IA186ES IA188ES F3 A4 – 8+8n 8+ – 8+8n 12+ – 8+8n 8+8n ...
Page 141
... Perform a signed division of r/m16 times Perform a signed division of r/m16 by 2, imm8 times Refer to the key for abbreviations and an explanation of notation ® Opcode – Hex Clock Cycles Byte Byte 1 Byte 2 3–6 IA186ES IA188ES D0 /1 – 2/15 2/ – 5+n/ 5+n/ 17+n 17 ...
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... Store AX in word ES:[DI]; update DI STOSB Store AL in byte ES:[DI]; update DI STOSW Store AX in word ES:[DI]; update DI Refer to the key for abbreviations and an explanation of notation ® Opcode – Hex Clock Cycles Byte Byte 1 Byte 2 3–6 IA186ES IA188ES 1C ib – data – 4/16 4/ – ...
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... XOR sign-extended imm8 with r/m16 XOR byte reg with r/m8 XOR word reg with r/m16 XOR r/m8 with byte reg XOR r/m16 with word reg ® Opcode – Hex Clock Cycles Byte Byte 1 Byte 2 3–6 IA186ES IA188ES 2C ib – – – ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 7.1 Key to Abbreviations Used in Instruction Set Summary Table Abbreviations used in the Instruction Set Summary Table 7.1.1 Operand Address Byte The operand address byte is configured as shown below mod field aux field r/m field 7.1.2 Modifier Field The modifier field is defined below. ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 7.1.4 r/m Field The r/m field is defined below. r/m Description 000 EA = (BX) + (SI) + DISP [where EA is the Effective Address] 001 EA = (BX) + (DI) + DISP 010 EA = (BP) + (SI) + DISP 011 EA = (BX) + (DI) + DISP 100 EA = (SI) + DISP 101 EA = (DI) + DISP 110 EA = (BP) + DISP [except if mod = 00, then EA = disp-high:disp-low] 111 EA = (BX) + DISP 7 ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 7.2 Explanation of Notation Used in Instruction Set Summary Table Notation used in the Instruction Set Summary Table Parameter Indication : The component of the left is the segment for a component located in memory. The component on the right is the offset. :: The component of the left is concatenated with the component on the right ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 7.2.2 Flags Affected After Instruction Flags affected after instruction are shown below. U Undefined - Unchanged R Result dependent ® IA211050902-15 UNCONTROLLED WHEN PRINTED OR COPIED Page 147 of 154 Data Sheet December 24, 2008 http://www.Innovasic.com Customer Support: 1-888-824-4184 ...
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... Innovasic/AMD Part Number Cross-Reference Tables Tables 90 and 91 show Innovasic part numbers cross-referenced with the corresponding AMD part number. Table 90. Innovasic/AMD Part Number Cross-Reference for the TQFP Innovasic Part Number IA186ES-PTQ100I-03 (standard packaging) IA186ES-PTQ100I-R-03 lead free (RoHS-compliant) IA188ES-PTQ100I-03 (standard packaging) IA188ES-PTQ100I-R-03 lead free (RoHS-compliant) ® ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Table 91. Innovasic/AMD Part Number Cross-Reference for the PQFP Innovasic Part Number IA186ES-PQF100I-03 (standard packaging) IA186ES-PQF100I-R-03 lead free (RoHS-compliant) IA188ES-PQF100I-03 (standard packaging) IA188ES-PQF100I-R-03 lead free (RoHS-compliant) ® AMD Part Number Package Type AM186ES-20KC\W 100-Pin Plastic Quad Flat AM186ES-25KC\W ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 9. Errata The following errata are associated with Version 03 of the IA186ES/IA188ES. A workaround to the identified problem has been provided where possible. 9.1 Errata Summary Table 92 presents a summary of errata. Table 92. Summary of Errata Errata No. 1 There is a difference in how priority of timer interrupts are asserted between the original AMD part and the Innovasic part ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Workaround: When using nested interrupts, at the beginning of the interrupt routine before the global interrupts are enabled with a CLI, timer interrupts must be specifically masked. At the end of the timer interrupt routine being serviced, set the Interrupt Enable Bit in the Process Status Word to globally disable interrupts prior to clearing the timer interrupt being serviced and unmask the appropriate timer interrupts ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers Errata No. 5 DMA interrupt will not bring device out of halt state. Problem: When device is in halt state, the interrupt caused by a DMA completion will not Description: bring the CPU out of the halt state. Use idle mode instead of halt. ...
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... IA186ES/IA188ES 8-Bit/16-Bit Microcontrollers 10. Revision History Table 93 presents the sequence of revisions to document IA211050902. Table 93. Revision History Date Revision August 17, 2007 11 January 31, 2008 12 February 19, 2008 13 August 7, 2008 14 December 24, 2008 15 ® Description Edition released. Errata 6 and 7 added. Errata 7 clarified. Column 2 of Peripheral Control Registers changed from ― ...
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... Microcontrollers 11. For Additional Information The IA186ES/IA188ES is a form, fit, and function replacement for the original AMD Am186ES/188ES family of microcontrollers. Innovasic produces replacement ICs using its MILES system cloning technology that produces replacement ICs far more complex than ―emulation‖ while ensuring they are compatible with the original IC. MILES captures the design of a clone so it can be produced even as silicon technology advances. MILES also verifies the clone against the original IC so that even the ― ...