ia186es Innovasic Semiconductor Inc., ia186es Datasheet - Page 31

• Manufacturer Part Number: ia186es
• Description: 8-bit/16-bit Microcontrollers
• Manufacturer: Innovasic Semiconductor Inc.

IA186ES/IA188ES
8-Bit/16-Bit Microcontrollers
2.2
2.2.1
These pins are the system’s source of non-multiplexed I/O or memory addresses and occur a half
clkouta cycle before the multiplexed address/data bus (ad15–ad0 for the IA186ES or ao15–ao8
and ad7–ad0 for the IA188ES).
The address bus is tristated during a bus hold or reset.
2.2.2
These pins are the system’s source of time-multiplexed I/O or memory addresses and data. The
address function of these pins may be disabled (see
address function of these pins is enabled, the address will be present on this bus during t
bus cycle and data will be present during t
If whb_n is not active, these pins are tristated during t
The address/data bus is tristated during a bus hold or reset.
These pins may be used to load the internal Reset Configuration register
with configuration data during a POR.
2.2.3
The address bus will contain valid high order address bits during the bus cycle (t
the bus is enabled by the AD bit in the Upper and Lower Memory Chip Select registers
offset
These pins are combined with ad7–ad0 to complete the multiplexed address bus and are tristated
during a bus hold or reset condition.
2.2.4
These pins are the system’s source of time-multiplexed low order byte of the addresses for I/O or
memory and 8-bit data. The low order address byte will be present on this bus during t
bus cycle and the 8-bit data will be present during t
The address function of these pins may be disabled (see
0a0h, and
Pin Descriptions
a19/pio9, a18/pio8, a17/pio7, a16–a0—Address Bus (synchronous outputs with
tristate)
ad15–ad8 (IA186ES)—Address/Data Bus (level-sensitive synchronous inouts with
tristate)
ao15–ao8 (IA188ES)—Address Bus (level-sensitive synchronous outputs with
tristate)
ad7–ad0—Address/Data Bus (level-sensitive synchronous inouts with tristate)
LMCS, offset
®
0a2h).
UNCONTROLLED WHEN PRINTED OR COPIED
2
, t
3
, and t
Page 31 of 154
IA211050902-15
2
bhe_n/aden_n pin
4
, t
of the same bus cycle.
2
3
, t
, and t
bhe_n/aden_n pin
3
, and t
4
of the same bus cycle.
4
of the bus cycle.
description). If the
(RESCON, offset
description).
December 24, 2008
http://www.Innovasic.com
1
, t
2
Customer Support:
, t
3
Data Sheet
1-888-824-4184
, and t
1
(UMCS,
1
of the
of the
0F6h)
4
) if