la-isppac-powr1014a Lattice Semiconductor Corp., la-isppac-powr1014a Datasheet - Page 35

• Manufacturer Part Number: la-isppac-powr1014a
• Description: In-system Programmable Power Supply Supervisor, Reset Generator And Sequencing Controller
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
User Electronic Signature
A user electronic signature (UES) feature is included in the E
This consists of 32 bits that can be configured by the user to store unique data such as ID codes, revision numbers
or inventory control data. The specifics of this feature are discussed in the IEEE 1149.1 serial interface section of
this data sheet.
Electronic Security
An electronic security “fuse” (ESF) bit is provided in every LA-ispPAC-POWR1014/A device to prevent unautho-
rized readout of the E
functional user bits in the device. This cell can only be erased by reprogramming the device, so the original config-
uration cannot be examined once programmed. Usage of this feature is optional. The specifics of this feature are
discussed in the IEEE 1149.1 serial interface section of this data sheet.
Production Programming Support
Once a final configuration is determined, an ASCII format JEDEC file can be created using the PAC-Designer soft-
ware. Devices can then be ordered through the usual supply channels with the user’s specific configuration already
preloaded into the devices. By virtue of its standard interface, compatibility is maintained with existing production
programming equipment, giving customers a wide degree of freedom and flexibility in production planning.
Evaluation Fixture
Because the features of an LA-ispPAC-POWR1014/A are all included in the larger ispPAC-POWR1220AT8 device,
designs implemented in an LA-ispPAC-POWR1014/A can be verified using an ispPAC-POWR1220AT8 engineering
prototype board connected to the parallel port of a PC with a Lattice ispDOWNLOAD
strates proper layout techniques and can be used in real time to check circuit operation as part of the design pro-
cess. Input and output connections are provided to aid in the evaluation of the functionality implemented in LA-
ispPAC-POWR1014/A for a given application. (Figure 5-29).
Figure 5-29. Download from a PC
IEEE Standard 1149.1 Interface (JTAG)
Serial Port Programming Interface Communication with the LA-ispPAC-POWR1014/A is facilitated via an IEEE
1149.1 test access port (TAP). It is used by the LA-ispPAC-POWR1014/A as a serial programming interface. A brief
description of the LA-ispPAC-POWR1014/A JTAG interface follows. For complete details of the reference specifica-
tion, refer to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1-1990
(which now includes IEEE Std 1149.1a-1993).
Overview
An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the LA-
ispPAC-POWR1014/A. The TAP controller is a state machine driven with mode and clock inputs. Given in the cor-
rect sequence, instructions are shifted into an instruction register, which then determines subsequent data input,
data output, and related operations. Device programming is performed by addressing the configuration register,
2
CMOS configuration bit patterns. Once programmed, this cell prevents further access to the
PAC-Designer
Software
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
5-35
ispDOWNLOAD
Cable (6')
2
CMOS memory of the LA-ispPAC-POWR1014/A.
4
POWR1220AT8
LA-ispPAC-
Circuitry
System
Other
Device
®
cable. The board demon-