la-isppac-powr1014a Lattice Semiconductor Corp., la-isppac-powr1014a Datasheet - Page 24

no-image

la-isppac-powr1014a

Manufacturer Part Number
la-isppac-powr1014a
Description
In-system Programmable Power Supply Supervisor, Reset Generator And Sequencing Controller
Manufacturer
Lattice Semiconductor Corp.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
la-isppac-powr1014a-01TN48E
Manufacturer:
LATTICE
Quantity:
171
Part Number:
la-isppac-powr1014a-01TN48E
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
Figure 5-15. LA-ispPAC-POWR1014A in I
In both the I
ter device generates the SCL clock signal and coordinates all data transfers to and from a number of slave devices.
The LA-ispPAC-POWR1014A is configured as a slave device, and cannot independently coordinate data transfers.
Each slave device on a given I
7-bit addressing portion of the standard. Any 7-bit address can be assigned to the LA-ispPAC-POWR1014A device
by programming through JTAG. When selecting a device address, one should note that several addresses are
reserved by the I
assure bus compatibility. Table 5-6 lists these reserved addresses.
Table 5-6. I
The LA-ispPAC-POWR1014A’s I
data write transaction (Figure 5-16) consists of the following operations:
1. Start the bus transaction
2. Transmit the device address (7 bits) along with a low write bit
3. Transmit the address of the register to be written to (8 bits)
4. Transmit the data to be written (8 bits)
5. Stop the bus transaction
SDA
V+
2
2
C/SMBus Reserved Slave Device Addresses
C and SMBus protocols, the bus is controlled by a single MASTER device at any given time. This mas-
0000 000
0000 000
0000 001
0000 010
0000 011
0000 1xx
0001 000
0001 100
0101 000
0110 111
1100 001
1111 0xx
1111 1xx
Address
MICROPROCESSOR
(I
2
2
SCL
C and/or SMBus standards, and should not be assigned to LA-ispPAC-POWR1014A devices to
C MASTER)
INTERRUPT
R/W bit
2
C bus is assigned a unique address. The LA-ispPAC-POWR1014A implements the
0
1
x
x
x
x
x
x
x
x
x
x
x
2
C/SMBus interface allows data to be both written to and read from the device. A
SDA/SMDAT (DATA)
SCL/SMCLK (CLOCK)
SMBALERT
General Call Address
Start Byte
CBUS Address
Reserved
Reserved
HS-mode master code
NA
NA
NA
NA
NA
10-bit addressing
Reserved
I
2
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
C function Description
2
C/SMBUS System
SDA
POWR1014A
(I
5-24
2
C SLAVE)
SCL
OUT5/
SMBA
General Call Address
Start Byte
CBUS Address
Reserved
Reserved
HS-mode master code
SMBus Host
SMBus Alert Response Address
Reserved for ACCESS.bus
Reserved for ACCESS.bus
SMBus Device Default Address
10-bit addressing
Reserved
SMBus Function
SDA
POWR1014A
(I
2
C SLAVE)
SCL
OUT5/
SMBA
To Other
Devices
I
2
C

Related parts for la-isppac-powr1014a