la-isppac-powr1014a Lattice Semiconductor Corp., la-isppac-powr1014a Datasheet - Page 21

• Manufacturer Part Number: la-isppac-powr1014a
• Description: In-system Programmable Power Supply Supervisor, Reset Generator And Sequencing Controller
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 5-11. LA-ispPAC-POWR1014/A Macrocell Block Diagram
Clock and Timer Functions
Figure 5-12 shows a block diagram of the LA-ispPAC-POWR1014/A’s internal clock and timer systems. The master
clock operates at a fixed frequency of 8MHz, from which a fixed 250kHz PLD clock is derived.
Figure 5-12. Clock and Timer System
The internal oscillator runs at a fixed frequency of 8 MHz. This signal is used as a source for the PLD and timer
clocks. It is also used for clocking the comparator outputs and clocking the digital filters in the voltage monitor cir-
PT4
PT3
PT2
PT1
PT0
Clock
Polarity
Block Init Product Term
Oscillator
Internal
8MHz
SW0
Global Polarity Fuse for
Init Product Term
SW1
MCLK
Product Term Allocation
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Global Reset
32
SW2
5-21
PLDCLK
Power On Reset
Timer 0
Timer 1
Timer 2
Timer 3
Macrocell flip-flop provides
D, T, or combinatorial
output with polarity
D/T
PLD Clock
R
CLK
To/From
P
Q
PLD
To PLD Output