la-isppac-powr1014a Lattice Semiconductor Corp., la-isppac-powr1014a Datasheet
la-isppac-powr1014a
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la-isppac-powr1014a Summary of contents
Page 1
... C/SMBus™ Compatible) Interface • Comparator status monitor • ADC readout • Direct control of inputs and outputs • Power sequence control • Only available with LA-ispPAC-POWR1014A ■ 3.3V Operation, Wide Supply Range 2.8V to 3.96V • In-system programmable through JTAG • Automotive temperature range: -40°C to +105°C • ...
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... The on-chip 10-bit A/D converter is used to monitor the V POWR1014A device. 2 The I C bus/SMBus interface allows an external microcontroller to measure the voltages connected to the V inputs, read back the status of each of the V control the output pins (LA-ispPAC-POWR1014A only). Figure 5-1. LA-ispPAC-POWR1014/A Block Diagram ADC* VMON1 VMON2 VMON3 ...
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... Sink Open-Drain Output 2 12.5µA to 100µA Source High-voltage FET Gate Driver 2 100µA to 3000µA Sink Open-Drain Output 3, (SMBUS Alert Active Low 5.5V LA-ispPAC-POWR1014A only 5.5V Open-Drain Output 5.5V Open-Drain Output 5.5V Open-Drain Output ...
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... JTAG Test Data In, TDISEL pin = 1 - Internal 0V to 5.5V Pull-up JTAG Test Data In (Alternate), TDISEL Pin = 5.5V Internal Pull- 5.5V Select TDI/ATDI Input - Internal Pull- 5.5V Only 5.5V (LA-ispPAC-POWR1014A Only) 2 C/SMBus interface (LA-ispPAC-POWR1014A only). 5-4 Description C Serial Clock Input (LA-ispPAC-POWR1014A C Serial Data, Bi-directional Pin, Open Drain ...
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... CCINP CCINP I JTAG supply current CCJ I Core and analog supply current CCPROG 1. Includes currents on V and V CCD CCA LA-ispPAC-POWR1014/A Automotive Family Data Sheet Parameter Conditions HVOUT[1:2] OUT[3:14] Conditions 2 During E programming pins OUT[3:14] pins HVOUT[1:2] pins in open-drain mode Power applied ...
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... IN V Range Programmable trip-point range MON V Sense Near-ground sense threshold Z V Accuracy Absolute accuracy of any trip-point MON Hysteresis of any trip-point (relative to HYST setting) 1. Guaranteed by characterization across V High Voltage FET Drivers Symbol Parameter V Gate driver output voltage PP Gate driver source current I OUTSRC ...
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... ADC Error Budget Across Entire Operating Temperature Range Symbol Parameter Total Measurement Error at TADC Error 2 Any Voltage 1. LA-ispPAC-POWR1014A only. 2. Total error, guaranteed by characterization, includes INL, DNL, Gain, Offset, and PSR specifications of the ADC. Power-On Reset Symbol Parameter T Delay from V to start-up state ...
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... Lattice Semiconductor Figure 5-2. LA-ispPAC-POWR1014/A Power-On Reset Reset State LA-ispPAC-POWR1014/A Automotive Family Data Sheet T BRO T T RST POR Start Up State T START Analog Calibration T GOOD 5-8 VCC RESETb MCLK PLDCLK AGOOD (Internal) ...
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... PLDCLK output frequency PLDCLK Timers Range of programmable Timeout Range timers (128 steps) Spacing between available Resolution adjacent timer intervals Accuracy Timer accuracy LA-ispPAC-POWR1014/A Automotive Family Data Sheet Over Recommended Operating Conditions Conditions f = 8MHz CLK f = 8MHz CLK f = 8MHz CLK 5-9 Min. ...
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... IN[1:4] referenced TDO, TDI, TMS, ATDI, TDISEL referenced to V CCINP 2. Sum of maximum current sink from all digital outputs combined. Reliable operation is not guaranteed if this value is exceeded. LA-ispPAC-POWR1014/A Automotive Family Data Sheet Over Recommended Operating Conditions Conditions HVOUT[1:2] in open drain mode and pulled ...
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... Device must be operational after power-on reset POR T Bus free time between stop and start condition BUF 1. Applies to LA-ispPAC-POWR1014A only less than 50kHz, then the ADC DONE status bit is not guaranteed to be set after a valid conversion request is completed. In this ...
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... VIH TCK VIL State Update-IR Run-Test/Idle (Erase) Figure 5-4. Programming Timing Diagram VIH TMS VIL SU1 H t CKH VIH TCK VIL State Update-IR LA-ispPAC-POWR1014/A Automotive Family Data Sheet Conditions SU1 CKH Select-DR Scan SU1 H SU1 CKL ...
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... Theory of Operation Analog Monitor Inputs The LA-ispPAC-POWR1014/A provides 10 independently programmable voltage monitor input circuits as shown in Figure 5-7. Two individually programmable trip-point comparators are connected to an analog monitoring input. Each comparator reference has 372 programmable trip points over the range of 0.672V to 5.867V. Additionally, a 75mV ‘ ...
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... LA-ispPAC-POWR1014/A Automotive Family Data Sheet LA-ispPAC-POWR1014/A Comp A/Window Select Comp A + – Comp B + – Window Control 5-14 To ADC (LA-ispPAC-POWR1014A on VMONxA Logic Signal Glitch Filter PLD Array VMONxB Logic Signal Glitch Filter Filtering VMONx Status ...
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... To monitor under-voltage fault conditions, the LTP should be used. Tables 1 and 2 show both the under-voltage and over-voltage trip points, which are automatically selected in soft- ware depending on whether the user is monitoring for an over-voltage condition or an under-voltage condition. LA-ispPAC-POWR1014/A Automotive Family Data Sheet UTP LTP ...
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... Low-V Sense LA-ispPAC-POWR1014/A Automotive Family Data Sheet Coarse Range Setting 1.360 1.612 1.923 2.290 1.353 1.603 1.913 2.278 1.346 1.595 1.903 2.266 1.338 1.586 1.893 2 ...
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... Low-V Sense LA-ispPAC-POWR1014/A Automotive Family Data Sheet 1.346 1.595 1.903 2.266 1.338 1.586 1.893 2.254 1.331 1.578 1.883 2.242 1.324 1.570 1.873 2.230 1.317 1 ...
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... Comp A Comp interface (LA-ispPAC-POWR1014A only). For details on the I 5- Window (B and Not A) Comment 0 Outside window, low 1 Inside window 0 Outside window, high ...
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... Lattice Semiconductor VMON Voltage Measurement with the On-chip Analog to Digital Converter (ADC, LA-ispPAC-POWR1014A Only) The LA-ispPAC-POWR1014A has an on-chip analog to digital converter that can be used for measuring the volt- ages at the VMON inputs. Figure 5-9. ADC Monitoring VMON1 to VMON10 VMON1 VMON2 VMON3 Programmable Analog ...
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... GLB1, GLB2, and GLB3. Each GLB is made up of eight macrocells. In total, there are 24 macrocells in the LA-ispPAC-POWR1014/A device. The output signals of the LA-ispPAC-POWR1014/A device are derived from GLBs as shown in Figure 5-10. GLB3 generates timer control ...
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... Oscillator 8MHz The internal oscillator runs at a fixed frequency of 8 MHz. This signal is used as a source for the PLD and timer clocks also used for clocking the comparator outputs and clocking the digital filters in the voltage monitor cir- LA-ispPAC-POWR1014/A Automotive Family Data Sheet ...
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... In addition to being usable as digital open-drain outputs, the LA-ispPAC-POWR1014/A’s HVOUT1-HVOUT2 output pins can be programmed to operate as high-voltage FET drivers. Figure 5-14 shows the details of the HVOUT gate drivers. Each of these outputs may be controlled from the PLD, or with the LA-ispPAC-POWR1014A, from the I bus (see Figure 5-14). For further details on controlling the outputs through I face section of this data sheet ...
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... SMBTimeout and SMBAlert features of the SMBus, enabling it to easily integrated into many types of modern power management systems. Figure 5-15 shows a typical I LA-ispPAC-POWR1014As are slaved to a supervisory microcontroller. SDA is used to carry data signals, while SCL provides a synchronous clock signal. The SMBAlert line is only present in SMBus systems. The 7-bit I address of the POWR1014A is fully programmable through the JTAG port ...
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... Each slave device on a given I C bus is assigned a unique address. The LA-ispPAC-POWR1014A implements the 7-bit addressing portion of the standard. Any 7-bit address can be assigned to the LA-ispPAC-POWR1014A device by programming through JTAG. When selecting a device address, one should note that several addresses are ...
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... The first frame contains the 7-bit device address with the R/W bit held High. In the second frame the LA-ispPAC-POWR1014A asserts data out on the bus in response to the SCL signal. Note that the acknowledge signal in the second frame is asserted by the master device and not the LA-ispPAC-POWR1014A. ...
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... VMON_STATUS2 (Read Only also possible to directly read the value of the voltage present on any of the VMON inputs by using the LA-isp- PAC-POWR1014A’s ADC. Three registers provide the I LA-ispPAC-POWR1014/A Automotive Family Data Sheet Description R VMON input status Vmon[4:1] R ...
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... When the conversion is complete, the result may be read out of the ADC by 2 performing two I C read operations; one for ADC_VALUE_LOW, and one for ADC_VALUE_HIGH recom- 2 mended that the I C master load a second conversion command only after the completion of the current conversion LA-ispPAC-POWR1014/A Automotive Family Data Sheet ...
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... To insure every ADC conversion result is valid, preferred operation is to clock I DONE bit status or wait for the full T request is placed before the current conversion is complete, the DONE bit will be set to 1 only after the second request is complete. The status of the digital input lines may also be monitored and controlled through I ...
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... OUTPUT_STATUS1 (Read Only 0x0E - GP_OUTPUT1 (Read/Write) GP8 GP7 b7 b6 0x0F - GP_OUTPUT2 (Read/Write The UES word may also be read through the I LA-ispPAC-POWR1014/A Automotive Family Data Sheet Configuration MUX 14 14 Output_Status0 Output_Status1 Interface Unit OUT6 ...
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... The I C interface also provides the ability to initiate reset operations. The LA-ispPAC-POWR1014A may be reset by issuing a write of any value to the I is equivalent to toggling the Resetb pin of the chip. Refer to the Resetb Signal, RESET Command via JTAG or I section of this data sheet for further information. ...
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... After OUT3/SMBA has been released, the bus master (typically a microcontroller) may opt to perform some service functions in which it may send data to or read data from the LA-ispPAC-POWR1014A. As part of the service func- tions, the bus master will typically need to clear whatever condition initiated the SMBAlert request, and will also need to reset GP3_ENb to re-enable the SMBAlert function ...
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... PAC-POWR1014/A elements via its graphical user interface. All analog input and output pins are represented. Static or non-configurable pins such as power, ground, and the serial digital interface are omitted for clarity. Any element in the schematic window can be accessed via mouse operations as well as menu commands. When com- pleted, confi ...
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... JTAG signal TDI. When the internally pulled-up TDISEL = 1, standard TDI pin is enabled and when the TDISEL = 0, ATDI is enabled. In order to use this feature the JTAG signals of the LA-ispPAC-POWR1014/A are connected to the header as shown in Figure 5-27. Note: The LA-ispPAC-POWR1014/A should be the last device in the JTAG chain. ...
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... VCCD and VCCA pins). In addition, to enable the on-chip JTAG interface circuitry, power should be applied to the VCCJ pin. When the LA-ispPAC-POWR1014/A is using the VCCPROG pin, its VCCD and VCCA pins can be open or pulled low. Additionally, other than JTAG I/O pins, all digital output pins are in Hi-Z state, HVOUT pins configured as MOS- FET driver are driven low, and all other inputs are ignored ...
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... LA-ispPAC-POWR1014/A can be verified using an ispPAC-POWR1220AT8 engineering prototype board connected to the parallel port with a Lattice ispDOWNLOAD strates proper layout techniques and can be used in real time to check circuit operation as part of the design pro- cess. Input and output connections are provided to aid in the evaluation of the functionality implemented in LA- ispPAC-POWR1014/A for a given application ...
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... In a given state, the controller responds according to the level on the TMS input as shown in Figure 5-31. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data Out (TDO) becoming valid on the falling edge of TCK. There are six steady states within the controller: Test-Logic-Reset, Run- Test/Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register and Pause-Instruction-Register ...
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... BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respec- tively). The LA-ispPAC-POWR1014/A contains the required minimum instruction set as well as one from the optional instruction set. In addition, there are several proprietary instructions that allow the device to be configured ...
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... The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI and TDO. The LA-ispPAC-POWR1014/A has no boundary scan register, so for compatibility it defaults to the BYPASS mode whenever this instruction is received. The bit code for this instruction is defined by Lattice as shown in Table 5-11. The EXTEST (external test) instruction is required and would normally place the device into an external boundary test mode while also enabling the boundary scan register to be connected between TDI and TDO ...
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... Part Number (20 bits) 00145h = LA-ispPAC-POWR1014A 10145h = LA-ispPAC-POWR1014 LA-ispPAC-POWR1014/A Specific Instructions There are 25 unique instructions specified by Lattice for the LA-ispPAC-POWR1014/A. These instructions are pri- marily used to interface to the various user registers and the E are used to control or monitor other features of the device ...
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... OUTPUTS_HIGHZ. OUTPUTS_HIGHZ – This instruction turns off all of the open-drain output transistors. Pins that are programmed as FET drivers will be placed in the active low state. This instruction is effective after Update-Instruction-Register JTAG state. PROGRAM_ENABLE – This instruction enables the programming mode of the LA-ispPAC-POWR1014/A. This instruction also forces the outputs into the OUTPUTS_HIGHZ. IDCODE – ...
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... ERASE_DONE_BIT – This instruction clears the ‘Done’ bit, which prevents the LA-ispPAC-POWR1014/A sequence from starting. PROGRAM_DONE_BIT – This instruction sets the ‘Done’ bit, which enables the LA-ispPAC-POWR1014/A sequence to start. RESET – This instruction resets the PLD sequence and output macrocells. ...
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... SECTION NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982. 2. ALL DIMENSIONS ARE IN MILLIMETERS. DATUMS A, B AND DETERMINED AT DATUM PLANE DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.254 AND E1 DIMENSIONS. 5. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM OF THE PACKAGE BY 0 ...
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... OUT11 OUT10 OUT9 GNDD OUT8 OUT7 OUT6 OUT5 OUT4 LA-ispPAC-POWR1014/A Automotive Family Data Sheet Package Lead-Free TQFP Lead-Free TQFP LA-ispPAC-POWR1014A 6 48-Pin TQFP 5-43 Operating Temperature Range Automotive (- +105 Package TN = Lead-Free 48-pin TQFP Performance Grade 01 = Standard ...
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... Products are not designed, intended or warranted to be fail-safe and are not designed, intended or warranted for use in applications related to the deployment of airbags. Further, products are not intended to be used, designed or warranted for use in applications that affect the control of the vehicle unless there is a fail-safe or redundancy fea- ture and also a warning signal to the operator of the vehicle upon failure ...
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... LA-ispPAC-POWR1014/A Automotive Family Data Sheet Change Summary Initial release. Added timing diagram and timing parameters to "Power-On Reset" specifications. Modified PLD Architecture figure to show input registers. 2 Updated I C Control Registers table. V pin usage clarification added. CCPROG Added automotive disclaimer text section. 5-45 ...