la-isppac-powr1014a Lattice Semiconductor Corp., la-isppac-powr1014a Datasheet - Page 23

• Manufacturer Part Number: la-isppac-powr1014a
• Description: In-system Programmable Power Supply Supervisor, Reset Generator And Sequencing Controller
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 5-14. Basic Function Diagram for an Output in High Voltage MOSFET Gate Driver Mode
Figure 5-14 shows the HVOUT circuitry when programmed as a FET driver. In this mode the output either sources
current from a charge pump or sinks current. The maximum voltage that the output level at the pin will rise to is also
programmable. The HVOUT pin source current, which is programmable between 12.5 µA and 100 µA, is used to
control the FET turn-on rate. Similarly, the HVOUT sink current, which is programmable between 3000 µA and 100
µA, is used to control the turn-off rate.
Programmable Output Voltage Levels for HVOUT1- HVOUT2
The HVOUT output voltage can be programmed to 6V or 8V when in FET driver mode.
RESETb Signal, RESET Command via JTAG or I
Activating the RESETb signal (Logic 0 applied to the RESETb pin) or issuing a reset instruction via JTAG, or with
the LA-ispPAC-POWR1014A, I
have been configured in the PINS window:
At the conclusion of the RESET event, these outputs will go to the states defined by the PINS window, and if a
sequence has been programmed into the device, it will be re-started at the first step. The analog calibration will be
re-done and consequently, the VMONs, and ADCs will not be operational until 500 microseconds (max.) after the
conclusion of the RESET event.
CAUTION: Activating the RESETb signal or issuing a RESET command through I2C or JTAG during the LA-isp-
PAC-POWR1014/A device operation, results in the device aborting all operations and returning to the power-on
reset state. The status of the power supplies which are being enabled by the LA-ispPAC-POWR1014/A will be
determined by the state of the outputs shown above.
I
I
devices on a circuit board. The LA-ispPAC-POWR1014A supports a 7-bit addressing of the I
protocol, as well as SMBTimeout and SMBAlert features of the SMBus, enabling it to easily integrated into many
types of modern power management systems. Figure 5-15 shows a typical I
LA-ispPAC-POWR1014As are slaved to a supervisory microcontroller. SDA is used to carry data signals, while
SCL provides a synchronous clock signal. The SMBAlert line is only present in SMBus systems. The 7-bit I
address of the POWR1014A is fully programmable through the JTAG port.
2
2
C and SMBus are low-speed serial interface protocols designed to enable communications among a number of
C/SMBUS Interface (LA-ispPAC-POWR1014A Only)
• OUT3-14 will go high-impedance.
• HVOUT pins programmed for open drain operation will go high-impedance.
• HVOUT pins programmed for FET driver mode operation will pull down.
(LA-ispPAC-POWR1014A Only)
Digital Control from I
Digital Control
from PLD
Charge Pump
2
C will force the outputs to the following states independent of how these outputs
(6 to 8V)
2
C Register
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
+
-
(100 to 500 µA)
+Fast Turn-off
(3000µA)
I
SINK
5-23
2
(12.5 to 100 µA)
C
I
SOURCE
HVOUTx
Pin
2
C configuration, in which one or more
Supply
Input
Load
2
C communications
2
C