ht82j30r Holtek Semiconductor Inc., ht82j30r Datasheet - Page 35

• Manufacturer Part Number: ht82j30r
• Description: Ht82j30r/ht82j30a -- 16 Channel A/d Mcu With Spi Interface
• Manufacturer: Holtek Semiconductor Inc.

; ADC interrupt service routine
ADC_ISR:
EXIT_INT_ISR:
A/D Transfer Function
As the device contain a 8-bit A/D converter, its full-scale
converted digitised value is equal to FFH. Since the
full-scale analog input value is equal to the VDD voltage,
this gives a single bit analog input value of V
diagram show the ideal transfer function between the
analog input value and the digitised output value for the
A/D converter.
Note that to reduce the quantisation error, a 0.5 LSB off-
set is added to the A/D Converter input. Except for the
digitised zero value, the subsequent digitised values will
change at a point 0.5 LSB below where they would
change without the offset, and the last full scale digitised
value will change at a point 1.5 LSB below the V
SPI Serial Interface
The device includes two SPI Serial Interfaces. The SPI
interface is a full duplex serial data link, originally de-
signed by Motorola, which allows multiple devices con-
nected to the same SPI bus to communicate with each
other. The devices communicate using a master/slave
technique where only the single master device can initi-
Rev. 1.10
mov acc_stack,a
mov a,STATUS
mov status_stack,a
mov a,ADR
mov adrl_buffer,a
mov a,status_stack
mov STATUS,a
mov a,acc_stack
reti
:
:
:
:
; save ACC to user defined memory
; save STATUS to user defined memory
; read conversion result value
; save result to user defined register
; restore STATUS from user defined memory
; restore ACC from user defined memory
DD
Ideal A/D Transfer Function
/256. The
DD
level.
35
ate a data transfer. A simple four line signal bus is used
for all communication.
SPI Interface Communication
Four lines are used for SPI communication known as
SDI - Serial Data Input, SDO - Serial Data Output, SCK -
Serial Clock and SCS - Slave Select. Note that the con-
dition of the Slave Select line is conditioned by the
CSEN bit in the SBCR control register. If the CSEN bit is
high then the SCS line is active while if the bit is low then
the SCS line will be in a floating condition. The following
timing diagram depicts the basic timing protocol of the
SPI bus.
SPI Registers
There are two registers associated with the SPI Inter-
face. These are the SBCR register which is the control
register and the SBDR which is the data register. The
SBCR register is used to setup the required setup pa-
rameters for the SPI bus and also used to store associ-
ated operating flags, while the SBDR register is used for
data storage.
HT82J30R/HT82J30A
March 13, 2008