ht82j30r Holtek Semiconductor Inc., ht82j30r Datasheet - Page 31

• Manufacturer Part Number: ht82j30r
• Description: Ht82j30r/ht82j30a -- 16 Channel A/d Mcu With Spi Interface
• Manufacturer: Holtek Semiconductor Inc.

the EOCB bit in the ADCR register will be set to a 1
and the analog to digital converter will be reset. It is the
START bit that is used to control the overall on/off oper-
ation of the internal analog to digital converter.
The EOCB bit in the ADCR register is used to indicate
when the analog to digital conversion process is com-
plete. This bit will be automatically set to 0 by the
microcontroller after a conversion cycle has ended. In
addition, the corresponding A/D interrupt request flag
will be set in the interrupt control register, and if the inter-
rupts are enabled, an appropriate internal interrupt sig-
nal will be generated. This A/D internal interrupt signal
will direct the program flow to the associated A/D inter-
nal interrupt address for processing. If the A/D internal
interrupt is disabled, the microcontroller can be used to
poll the EOCB bit in the ADCR register to check whether
it has been cleared as an alternative method of detect-
ing the end of an A/D conversion cycle.
A/D Converter Clock Source Register - ACSR
The clock source for the A/D converter, which originates
Rev. 1.10
A/D Converter Control Register
A/D Converter Structure
31
from the system clock f
ratio, the value of which is determined by the ADCS1
and ADCS0 bits in the ACSR register.
The ACSR control register also contains the
PCR3~PCR0 bits which determine which pins on Port B
and Port C are used as analog inputs for the A/D con-
verter and which pins are to be used as normal I/O pins.
If the 3-bit address on PCR3~PCR0 has a value of
and AN15 will all be set as analog inputs. Note that if the
PCR3~PCR0 bits are all set to zero, then all the Port B
and Port C pins will be setup as normal I/Os and the inter-
nal A/D converter circuitry will be powered off to reduce
the power consumption.
Although the A/D clock source is determined by the sys-
tem clock f
some limitations on the maximum A/D clock source speed
that can be selected. As the minimum value of permissible
A/D clock period, t
tem clock speeds in excess of 4MHz. For system clock
speeds in excess of 4MHz, the ADCS1 and ADCS0 bits
1111 or higher, then all 16 pins, namely AN0, AN1, AN2
SYS
, and by bits ADCS1 and ADCS0, there are
AD
, is 0.5 s, care must be taken for sys-
HT82J30R/HT82J30A
SYS
, is first divided by a division
March 13, 2008