ht82j30r Holtek Semiconductor Inc., ht82j30r Datasheet - Page 20

• Manufacturer Part Number: ht82j30r
• Description: Ht82j30r/ht82j30a -- 16 Channel A/d Mcu With Spi Interface
• Manufacturer: Holtek Semiconductor Inc.

Interrupts
Interrupts are an important part of any microcontroller
system. When an external interrupt pin transition or an
internal function such as a Timer/Event Counter over-
flow, an A/D converter conversion, or transmission or re-
ception of SPI data occurs, their corresponding interrupt
will enforce a temporary suspension of the main pro-
gram allowing the microcontroller to direct attention to
their respective needs. Each device contains two exter-
nal interrupts and several internal interrupts functions.
The external interrupt is controlled by the action of the
external interrupt pins, while the internal interrupts are
controlled by the Timer/Event Counter overflow, the A/D
converter and SPI data transmission or reception.
Interrupt Register
Overall interrupt control, which means interrupt enabling
and request flag setting, is controlled by the two inter-
rupt control registers, which are located in the Data
Memory. By controlling the appropriate enable bits in
these registers each individual interrupt can be enabled
or disabled. Also when an interrupt occurs, the corre-
sponding request flag will be set by the microcontroller.
The global enable flag if cleared to zero will disable all
interrupts.
Interrupt Operation
An A/D converter end of conversion, a Timer/Event
Counter overflow, 8-bits of data transmission or recep-
tion on either of the two SPI interfaces or an active edge
on any of the two external interrupt pins will all generate
an interrupt request by setting their corresponding re-
quest flag, if their appropriate interrupt enable bit is set.
When this happens, the Program Counter, which stores
the address of the next instruction to be executed, will
be transferred onto the stack. The Program Counter will
then be loaded with a new address which will be the
value of the corresponding interrupt vector. The
microcontroller will then fetch its next instruction from
this interrupt vector. The instruction at this vector will
usually be a JMP statement which will jump to another
section of program which is known as the interrupt ser-
vice routine. Here is located the code to control the ap-
propriate interrupt. The interrupt service routine must be
terminated with a RETI statement, which retrieves the
original Program Counter address from the stack and al-
lows the microcontroller to continue with normal execu-
tion at the point where the interrupt occurred.
The various interrupt enable bits, together with their as-
sociated request flags, are shown in the accompanying
diagram with their order of priority.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked, as the EMI bit will be cleared au-
tomatically. This will prevent any further interrupt nesting
from occurring. However, if other interrupt requests oc-
cur during this interval, although the interrupt will not be
Rev. 1.10
20
immediately serviced, the request flag will still be re-
corded. If an interrupt requires immediate servicing
while the program is already in another interrupt service
routine, the EMI bit should be set after entering the rou-
tine, to allow interrupt nesting. If the stack is full, the in-
terrupt request will not be acknowledged, even if the
related interrupt is enabled, until the Stack Pointer is
decremented. If immediate service is desired, the stack
must be prevented from becoming full.
Interrupt Priority
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In case of simultaneous requests,
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
In cases where both external and internal interrupts are
enabled and where an external and internal interrupt oc-
curs simultaneously, the external interrupt will always
have priority and will therefore be serviced first. Suitable
masking of the individual interrupts using the interrupt
registers can prevent simultaneous occurrences.
External Interrupt
For an external interrupt to occur, the global interrupt en-
able bit, EMI, and external interrupt enable bit, EEI_A, or
EEI_B must first be set. An actual external interrupt will
take place when the external interrupt request flag,
EIF_A or EIF_B is set, a situation that will occur when a
high to low transition appears on the interrupt pins. The
external interrupt pin is pin-shared with the I/O pins PA5
and PA6 and can only be configured as an external in-
terrupt pin if the corresponding external interrupt enable
bits in the interrupt control register INTC0 and INTC1
have been set. The pins must also be setup as inputs by
setting the corresponding PAC.5 and PAC.6 bits in the
port control register. When the interrupt is enabled, the
stack is not full and a high to low transition appears on
the external interrupt pin, a subroutine call to the exter-
nal interrupt vector at location 04H or 018H will take
place. When the interrupt is serviced, the external inter-
rupt request flag, EIF_A or EIF_B will be automatically
reset and the EMI bit will be automatically cleared to dis-
External Interrupt INT0
Timer/Event Counter Overflow
Interrupt
End of A/D Converter Interrupt
SPI_A Interrupt
SPI_B Interrupt
External Interrupt INT1
Interrupt Source
HT82J30R/HT82J30A
Priority
1
2
3
4
5
6
March 13, 2008
000CH
Vector
0004H
0008H
0010H
0014H
0018H