ht82j30r Holtek Semiconductor Inc., ht82j30r Datasheet - Page 28

• Manufacturer Part Number: ht82j30r
• Description: Ht82j30r/ht82j30a -- 16 Channel A/d Mcu With Spi Interface
• Manufacturer: Holtek Semiconductor Inc.

No matter what the source of the wake-up event is, once
a wake-up situation occurs, a time period equal to 1024
system clock periods will be required before normal sys-
tem operation resumes. However, if the wake-up has
originated due to an interrupt, the actual interrupt sub-
routine execution will be delayed by an additional one or
more cycles. If the wake-up results in the execution of
the next instruction following the HALT instruction, this
will be executed immediately after the 1024 system
clock period delay has ended.
Watchdog Timer
The Watchdog Timer is provided to prevent program
malfunctions or sequences from jumping to unknown lo-
cations, due to certain uncontrollable external events
such as electrical noise. It operates by providing a de-
vice reset when the WDT counter overflows. The WDT
clock is supplied by one of two sources selected by con-
figuration option: its own self contained dedicated inter-
nal WDT oscillator or f
configuration option has been disabled, then any instruc-
tion relating to its operation will result in no operation.
All Watchdog Timer options, such as enable/disable,
WDT clock source and clear instruction type all selected
through configuration options. There are no internal reg-
isters associated with the WDT in this device. One of the
WDT clock sources is an internal oscillator which has an
approximate period of 65 s at a supply voltage of 5V.
However, it should be noted that this specified internal
clock period can vary with VDD, temperature and pro-
cess variations. The other WDT clock source option is
the f
own internal WDT oscillator, or from f
divided by an internal 15-bit counter and a clearable sin-
gle bit counter to give longer Watchdog time-outs. As
this ratio is fixed it gives an overall Watchdog Timer
time-out value of 2
only resets the last stage of the divider chain, for this
reason the actual division ratio and corresponding
Watchdog Timer time-out can vary by a factor of two.
Rev. 1.10
SYS
/4 clock. Whether the WDT clock source is its
15
/f
S
to 2
SYS
16
/4. Note that if the WDT
/f
S
. As the clear instruction
SYS
/4, it is further
Watchdog Timer
28
The exact division ratio depends upon the residual value
in the Watchdog Timer counter before the clear instruc-
tion is executed. It is important to realise that as there
are no independent internal registers or configuration
options associated with the length of the Watchdog
Timer time-out, it is completely dependent upon the fre-
quency of f
If the f
should be noted that when the system enters the Power
Down Mode, then the instruction clock is stopped and
the WDT will lose its protecting purposes. For systems
that operate in noisy environments, using the internal
WDT oscillator is strongly recommended.
Under normal program operation, a WDT time-out will
initialise a device reset and set the status bit TO. How-
ever, if the system is in the Power Down Mode, when a
WDT time-out occurs, the TO bit in the status register
will be set and only the Program Counter and Stack
Pointer will be reset. Three methods can be adopted to
clear the contents of the WDT. The first is an external
hardware reset, which means a low level on the RES
pin, the second is using the watchdog software instruc-
tions and the third is via a HALT instruction.
There are two methods of using software instructions to
clear theWatchdog Timer, one of which must be chosen
by configuration option. The first option is to use the sin-
gle CLR WDT instruction while the second is to use the
two commands CLR WDT1 and CLR WDT2. For the first
option, a simple execution of CLR WDT will clear the
WDT while for the second option, both CLR WDT1 and
CLR WDT2 must both be executed to successfully clear
the WDT. Note that for this second option, if CLR WDT1
is used to clear the WDT, successive executions of this
instruction will have no effect, only the execution of a
CLR WDT2 instruction will clear the WDT. Similarly after
the CLR WDT2 instruction has been executed, only a
successive CLR WDT1 instruction can clear the Watch-
dog Timer.
SYS
/4 clock is used as the WDT clock source, it
SYS
/4 or the internal WDT oscillator.
HT82J30R/HT82J30A
March 13, 2008