ht82j30r Holtek Semiconductor Inc., ht82j30r Datasheet
ht82j30r
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ht82j30r Summary of contents
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... A/D converter Single channel (6+2)-bit PWM output shared with an I/O line General Description The HT82J30R and HT82J30A are 8-bit high perfor- mance, RISC architecture microcontroller devices spe- cifically designed for A/D applications that interface directly to analog signals, such as those from sensors. ...
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... Block Diagram Pin Assignment Rev. 1.10 HT82J30R/HT82J30A 2 March 13, 2008 ...
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... If the RC system clock is selected, pin OSC2 can be used to measure the system clock at 1/4 frequency. Schmitt trigger reset input. Active low Negative power supply, ground Positive power supply 8-bit A/D reference voltage input pin 3 HT82J30R/HT82J30A March 13, 2008 ...
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... I/O Port Sink Current OL I I/O Port Source Current OH R Pull-high Resistance PH V A/D Input Voltage AD E A/D Conversion Error AD Only ADC Enable, I ADC Others Disable Rev. 1.10 HT82J30R/HT82J30A +6.0V Storage Temperature ............................ 125 C SS +0.3V Operating Temperature........................... Total............................................................ 100mA OH Test Conditions Min. V Conditions DD f =4MHz 2.2 SYS 2 ...
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... Interrupt Pulse Width INT t A/D Clock Period AD t A/D Conversion Time ADC t A/D Sample Time ADCS t SPI SCS to SCK Time CS_SK t SPI Clock Time SPICK Note: t =1/f or 1/f SYS SYS1 SYS2 Rev. 1.10 HT82J30R/HT82J30A Test Conditions Min. V Conditions DD 2.2V~2.7V 400 2.8V~5.5V 400 2.7V~5.5V 1000 2.2V~2.7V 0 2.8V~5. ...
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... Program Counter Low Register, are directly addressable by user. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the System Clocking and Pipelining Instruction Fetching 6 HT82J30R/HT82J30A March 13, 2008 ...
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... PCL bits #11~#0: Instruction code address bits S11~S0: Stack register bits Rev. 1.10 HT82J30R/HT82J30A Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the ac- knowledge signal will be inhibited ...
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... SIZA, SDZA, CALL, RET, RETI Program Memory The Program Memory is the location where the user code or program is stored. The HT82J30R is a One-Time Programmable, OTP, memory type device where users can program their application code into the device. By using the appropriate programming tools, ...
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... Note: PC11~PC8: Current Program Counter bits @7~@0: Table Pointer TBLP bits Rev. 1.10 HT82J30R/HT82J30A Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data lo- cated in the last page which is stored there using the ORG statement ...
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... SET [m].i and CLR [m].i with the exception of a few dedicated bits. The Data Memory can also be accessed through the memory pointer register MP. Rev. 1.10 HT82J30R/HT82J30A microcontrollers, such as ACC, PCL, etc., have the same Data Memory address. General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later ...
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... The important point to note here is that in the example shown above, no reference is made to specific Data Memory ad- dresses. Rev. 1.10 HT82J30R/HT82J30A where the actual memory address is defined. Any ac- tions on the IAR register will result in corresponding read/write operations to the memory location specified by the Memory Pointer MP. Reading the IAR register in- directly will return a result of 00H and writing to the register indirectly will result in no operation ...
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... Note that the lower order table data byte is transferred to a user de- fined location. Rev. 1.10 HT82J30R/HT82J30A Status Register - STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). ...
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... I/O control registers during normal pro- gram operation is a useful feature of these devices. Rev. 1.10 HT82J30R/HT82J30A Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of ev- ery pin fully under user program control, pull-high op- ...
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... I/O pin, however to do this, the external interrupt enable bits in the INTC1 register must be disabled. Rev. 1.10 HT82J30R/HT82J30A Input/Output Ports External Timer Clock Input The external timer pin TMR is pin-shared with the I/O pin PA4. To configure this pin to operate as timer input, the corresponding control bits in the timer control reg- ister must be correctly set ...
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... Read/Write Timing 8-bit Timer/Event Counter Structure Rev. 1.10 HT82J30R/HT82J30A Port A has the additional capability of providing wake-up functions. When the device is in the Power Down Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins ...
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... TMR register, these two registers control the full operation of the Timer/Event Counter. Before the Timer/Event Counter Control Register Rev. 1.10 HT82J30R/HT82J30A timer can be used essential that the TMRC register is fully programmed with the right data to ensure its cor- rect operation, a process that is normally carried out during program initialisation ...
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... Measurement Mode, the TON bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the TON bit can only be reset to zero under Timer Mode Timing Chart Event Counter Mode Timing Chart 17 HT82J30R/HT82J30A March 13, 2008 ...
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... The PFD output will only be activated if bit PA3 is set This output data bit is used as the Rev. 1.10 HT82J30R/HT82J30A on/off control bit for the PFD output. Note that the PFD output will be low if the PA3 output data bit is cleared to 0 ...
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... Timer/Event Counter - note mode bits must be previously setup Rev. 1.10 HT82J30R/HT82J30A When the Timer/Event counter overflows, its corre- sponding interrupt request flag in the interrupt control register will be set. If the timer interrupt is enabled this will in turn generate an interrupt signal. However irre- ...
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... This will prevent any further interrupt nesting from occurring. However, if other interrupt requests oc- cur during this interval, although the interrupt will not be Rev. 1.10 HT82J30R/HT82J30A immediately serviced, the request flag will still be re- corded interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the rou- tine, to allow interrupt nesting ...
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... Rev. 1.10 HT82J30R/HT82J30A INTC0 Register INTC1 Register 21 March 13, 2008 ...
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... When the interrupt is serviced, the SPI interrupt request flag, SIF_A or SIF_B, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Rev. 1.10 HT82J30R/HT82J30A Interrupt Structure A/D Interrupt For an A/D converter interrupt to occur, the global inter- rupt enable bit, EMI, and the corresponding A/D con- verter interrupt enable flag, EADI, must first be set ...
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... In such cases it is recom- Rev. 1.10 HT82J30R/HT82J30A mended that an external RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise ...
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... Watchdog time-out flag TO will be set WDT Time-out Reset during Normal Operation Timing Chart Rev. 1.10 HT82J30R/HT82J30A Watchdog Time-out Reset during Power Down The Watchdog time-out Reset during Power Down is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Pro- gram Counter and the Stack Pointer will be cleared to 0 and the TO flag will be set to 1 ...
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... HT82J30R/HT82J30A RES Reset WDT Time-out (HALT) (HALT)* uuuu uuuu uuuu uuuu 000H 000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ...
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... Resonator 300pF Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure Rev. 1.10 HT82J30R/HT82J30A that the V is stable and remains within a valid DD operating voltage range before bringing RES to high. * Make the length of the wiring, which is con- nected to the RES pin as short as possible, to avoid noise interface ...
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... CMOS inputs. Rev. 1.10 HT82J30R/HT82J30A If the configuration options have enabled the Watchdog Timer internal oscillator then this will continue to run when in the Power Down Mode and will thus consume some power ...
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... CLR WDT2 instruction will clear the WDT. Similarly after the CLR WDT2 instruction has been executed, only a successive CLR WDT1 instruction can clear the Watch- dog Timer. Watchdog Timer 28 HT82J30R/HT82J30A March 13, 2008 ...
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... PWM output. The difference between what is known as the PWM cycle frequency and the PWM modulation fre- Rev. 1.10 HT82J30R/HT82J30A quency should be understood. As the PWM clock is the system clock and as the PWM value is 8-bits wide, ...
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... A/D converter. When the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. When the START bit is brought from low to high but not low again, 30 HT82J30R/HT82J30A Input Pins PB0~PB3 8-bit PC1, PC2 ...
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... A/D clock source speed that can be selected. As the minimum value of permissible A/D clock period 0.5 s, care must be taken for sys- AD tem clock speeds in excess of 4MHz. For system clock speeds in excess of 4MHz, the ADCS1 and ADCS0 bits 31 HT82J30R/HT82J30A , is first divided by a division SYS March 13, 2008 ...
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... The internal A/D converter must be initialised in a spe- cial way. Each time the Port B and Port C A/D channel selection bits are modified by the program, the A/D con- verter must be re-initialised. If the A/D converter is not initialised after the channel selection bits are changed, 32 HT82J30R/HT82J30A ADCS1, ADCS0=11 Undefined Undefined Undefined Undefined ...
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... Step 5 The analog to digital conversion process can now be initialised by setting the START bit in the ADCR regis- Rev. 1.10 HT82J30R/HT82J30A A/D Conversion Timing ter from and then to 0 again. Note that this bit should have been originally set Step 6 To check when the analog to digital conversion pro- cess is complete, the EOCB bit in the ADCR register can be polled ...
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... ADCR register to configure Port PB0~PB3 ; as A/D inputs ; and select AN0 to be connected to the A the Port B channel bits have changed the ; following START signal must be issued ; within 10 instruction cycles ; reset A/D ; start A/D ; clear ADC interrupt request flag ; enable ADC interrupt ; enable global interrupt 34 HT82J30R/HT82J30A March 13, 2008 ...
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... These are the SBCR register which is the control register and the SBDR which is the data register. The SBCR register is used to setup the required setup pa- rameters for the SPI bus and also used to store associ- ated operating flags, while the SBDR register is used for data storage. 35 HT82J30R/HT82J30A March 13, 2008 ...
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... Rev. 1.10 HT82J30R/HT82J30A SPI Block Diagram 36 March 13, 2008 ...
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... If in the Slave Mode the SCK line will floating condition. If SBEN is low then the bus will be disabled and SCS, SDI, SDO and SCK will all floating condition. SPI Interface Control Register SPI Bus Timing 37 HT82J30R/HT82J30A March 13, 2008 ...
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... TXRX register, then wait for the master clock and SCS signal. After this goto step 6. Rev. 1.10 HT82J30R/HT82J30A For read operations: the data transferred in on the SDI line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SBDR register ...
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... SPI_A WCOL bit: enable or disable SPI_A CSEN bit: enable or disable SPI_A SCK clock polarity: rising edge or falling edge SPI_B: enable or disable SPI_B WCOL bit: enable or disable SPI_B CSEN bit: enable or disable SPI_B SCK clock polarity: rising edge or falling edge Rev. 1.10 HT82J30R/HT82J30A Options 39 March 13, 2008 ...
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... Application Circuits Rev. 1.10 HT82J30R/HT82J30A 40 March 13, 2008 ...
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... Within the Holtek microcontroller instruction set are a range of add and Rev. 1.10 HT82J30R/HT82J30A subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to en- sure correct handling of carry and borrow data when re- sults exceed 255 for addition and less than 0 for subtraction ...
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... DECA [m] Decrement Data Memory with result in ACC DEC [m] Decrement Data Memory Rev. 1.10 HT82J30R/HT82J30A Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT in- struction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electro- magnetic environments ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.10 HT82J30R/HT82J30A Description 43 Cycles Flag Affected ...
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... Operation ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev. 1.10 HT82J30R/HT82J30A 44 March 13, 2008 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev. 1.10 HT82J30R/HT82J30A addr 45 March 13, 2008 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev. 1. HT82J30R/HT82J30A March 13, 2008 ...
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... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev. 1.10 HT82J30R/HT82J30A addr 47 March 13, 2008 ...
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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev. 1.10 Stack Stack Stack [m]. 0~6) 48 HT82J30R/HT82J30A March 13, 2008 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev. 1.10 [m]. 0~6) 49 HT82J30R/HT82J30A March 13, 2008 ...
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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev. 1.10 [ HT82J30R/HT82J30A March 13, 2008 ...
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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev. 1.10 0 [m] [ HT82J30R/HT82J30A March 13, 2008 ...
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... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev. 1.10 HT82J30R/HT82J30A [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 52 March 13, 2008 ...
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... The result is stored in the Data Memory. Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev. 1.10 HT82J30R/HT82J30A 53 March 13, 2008 ...
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... Package Information 28-pin SKDIP (300mil) Outline Dimensions Symbol Rev. 1.10 Dimensions in mil Min. Nom. 1375 278 125 125 16 50 100 295 330 0 54 HT82J30R/HT82J30A Max. 1395 298 135 145 20 70 315 375 15 March 13, 2008 ...
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... SOP (300mil) Outline Dimensions Symbol Rev. 1.10 Dimensions in mil Min. Nom. 394 290 14 697 HT82J30R/HT82J30A Max. 419 300 20 713 104 March 13, 2008 ...
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... QFP (10´10) Outline Dimensions Symbol Rev. 1.10 Dimensions in mm Min. Nom. 13 9.9 13 9.9 0.8 0.3 1.9 0.25 0.73 0.1 0 HT82J30R/HT82J30A Max. 13.4 10.1 13.4 10.1 2.2 2.7 0.5 0.93 0.2 7 March 13, 2008 ...
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... Product Tape and Reel Specifications Reel Dimensions SOP 28W (300mil) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.10 HT82J30R/HT82J30A Dimensions in mm 330 1 62 1.5 13+0.5 0.2 2 0.5 24.8+0.3 0.2 30.2 0.2 57 March 13, 2008 ...
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... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.10 HT82J30R/HT82J30A Dimensions 0.3 12 0.1 1.75 0.1 11.5 0.1 1.5+0.1 1.5+0.25 4 0.1 2 0.1 10.85 0.1 18.34 0.1 2.97 0.1 0.35 0.01 21.3 58 March 13, 2008 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.10 HT82J30R/HT82J30A 59 March 13, 2008 ...