ht82a836r Holtek Semiconductor Inc., ht82a836r Datasheet - Page 46

• Manufacturer Part Number: ht82a836r
• Description: Usb Audio Mcu
• Manufacturer: Holtek Semiconductor Inc.

SPI Serial Interface
The device includes a single SPI Serial Interface. The
SPI interface is a full duplex serial data link, originally
designed by Motorola, which allows multiple devices
connected to the same SPI bus to communicate with
each other. The devices communicate using a mas-
ter/slave technique where only the single master device
can initiate a data transfer. A simple four line signal bus
is used for all communication.
SPI Interface Communication
Four lines are used for SPI communication known as
SDI - Serial Data Input, SDO - Serial Data Output, SCK
condition of the Slave Select line is conditioned by the
CSEN bit in the SBCR control register. If the CSEN bit is
high then the SCS line is active while if the bit is low then
the SCS line will be in a floating condition. The following
timing diagram depicts the basic timing protocol of the
SPI bus.
SPI Registers
There are two registers associated with the SPI Inter-
face. These are the SBCR register which is the control
register and the SBDR which is the data register. The
SBCR register is used to setup the required setup pa-
rameters for the SPI bus and also used to store associ-
ated operating flags, while the SBDR register is used for
data storage.
Rev. 1.00
Serial Clock and SCS
Slave Select. Note that the
SPI Block Diagram
46
After Power on, the contents of the SBDR register will be
in an unknown condition while the SBCR register will de-
fault to the condition below:
Note that data written to the SBDR register will only be
written to the TXRX buffer, whereas data read from the
SBDR register will actually be read from the register.
SPI Bus Enable/Disable
To enable the SPI bus then CSEN=1 and SBEN=1, the
SCK, SDI, SDO and SCS lines should all be zero, then
wait for data to be written to the SBDR (TXRX buffer)
register. For the Master Mode, after data has been writ-
ten to the SBDR (TXRX buffer) register then transmis-
sion or reception will start automatically. When all the
data has been transferred the TRF bit should be set. For
the Slave Mode, when clock pulses are received on
SCK, data in the TXRX buffer will be shifted out or data
on SDI will be shifted in.
To Disable the SPI bus SCK, SDI, SDO, SCS floating.
SPI Operation
All communication is carried out using the 4-line inter-
face for both Master or Slave Mode. The timing diagram
shows the basic operation of the bus.
CKS
0
M1
1
M0 SBEN MLS CSEN WCOL TRF
1
0
0
HT82A836R
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March 20, 2008
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