ht82a836r Holtek Semiconductor Inc., ht82a836r Datasheet
ht82a836r
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ht82a836r Summary of contents
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... Low voltage reset function (3.0V 0.3V) 80-pin LQFP (10mm 10mm) and 100-pin QFP package types The DAC in the HT82A836R operates at a sampling rate of 48kHz/8kHz and the 16-bit PCM ADC operates at frequency of 8kHz/16kHz for the Microphone input, with the options selected using software. The integrated DAC also includes a digitally programmable gain ampli- fier with a range of 32dB to +6dB ...
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... Block Diagram Pin Assignment Rev. 1.00 2 HT82A836R March 20, 2008 ...
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... ROUT and LOUT at the same time. AVDD4 12-bit ADC positive power supply AVDD3 PCM ADC positive power supply AVDD2 Audio power amplifier positive power supply AVDD1 Audio DAC positive power supply Rev. 1.00 Description 3 HT82A836R March 20, 2008 ...
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... Negative digital power supply, ground OSCI I OSCI, OSCO are connected to an 6MHz or 12MHz crystal/resonator, OSCO O determined by software instructions, for the internal system clock. RESET I Schmitt trigger reset input, active low USBDN I/O USBD- line USBDP I/O USBD+ line V33O O 3.3V regulator output Rev. 1.00 Description 4 HT82A836R March 20, 2008 ...
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... 2 5mA 3.0 V33O = 48kHz. Line output series capacitor with 220 load 5V 8 load 4 load 5V 8 load 4 load 5V 8 load 4 load, THD=10 load, THD=10 HT82A836R Ta=25 C Typ. Max. Unit 5.0 5 330 ...
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... RES t System Start-up Timer Period SST t Interrupt Pulse Width INT t A/D Conversion Time ADC t A/D Sampling Time ADCS Note: *t =1/f SYS SYS Rev. 1.00 Test Conditions Min. V Conditions HT82A836R Ta=25 C Typ. Max. Unit 12 MHz 100 1024 SYS March 20, 2008 ...
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... JMP or CALL , that demand a jump to a non-consecutive Program Memory address. Note that the Program Counter width varies with the Program Memory capacity depending upon which device is se- lected. System Clocking and Pipelining Instruction Fetching 7 HT82A836R March 20, 2008 ...
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... Program Counter + # S10 Program Counter 8 HT82A836R ...
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... Location 018H This area is used by the Record interrupt. If record data occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full. Program Memory Structure 9 HT82A836R March 20, 2008 ...
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... However, in situations where simultaneous use cannot be avoided, the inter- rupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. 10 HT82A836R March 20, 2008 ...
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... Data Memory address is FFH. The Bank 1 Data Memory consists only of General Purpose Data Memory. The start address of the Bank 1 Data Memory is the address 40H and the last Data Memory address is FFH. Selection of which Bank used is implemented using the Bank Pointer. 11 HT82A836R ...
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... Special Function Register section. Note that for lo- cations that are unused, any read instruction to these addresses will return the value 00H . Rev. 1.00 Special Purpose Data Memory Structure 12 HT82A836R March 20, 2008 ...
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... The following example shows how to clear a section of four RAM locations already defined as locations adres1 to adres4. ; setup size of block ; setup memory pointer with first RAM address ; clear the data at address defined by MP0 ; increment memory pointer ; check if last memory location has been cleared 13 HT82A836R March 20, 2008 ...
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... With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, opera- Bank Pointer 14 HT82A836R March 20, 2008 ...
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... One flexible feature of these registers is the ability to directly program single bits using the SET [m].i and CLR [m].i instructions. The ability to change I/O pins from output to input and vice versa by manipulating spe- cific bits of the I/O control registers during normal pro- gram operation is a useful feature of these devices. 15 HT82A836R March 20, 2008 ...
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... This option is provided using the PA_WAKE_CTRL reg- ister. Only Port A pins have this feature, the wake-up pins on the other ports are only negative edge triggered. 16 HT82A836R March 20, 2008 ...
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... I/O pins or as SPI Interface pins. I/O Pin Structures The following diagrams illustrate the I/O pin internal structures. As the exact logical construction of the I/O pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. 17 HT82A836R March 20, 2008 ...
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... Timer/Event Counter control registers, which define the timer options, and determines how the timers are to be used. The timer clock source can be configured to come from the internal system clock source or from an external clock on shared pin PC1/TMR0 and PC2/TMR1. 18 HT82A836R March 20, 2008 ...
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... The timer will count from the initial value loaded by the preload register to the full count of FFFFH at which point the timer overflows and an internal inter- rupt signal is generated. The timer value will then be re- 19 HT82A836R March 20, 2008 ...
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... Timer/Event Counter to run, clear- ing the bit stops it running. If the Timer/Event Counter is in the event count or pulse width measurement mode, the active transition edge level type is selected by the logic level of bit 3 of the Timer control Register which is known as TE. 20 HT82A836R March 20, 2008 ...
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... As before, the enable bit will be automatically reset to zero and the Timer/Event Counter will stop counting important to note that in the Pulse Width Measurement Mode, the Timer Mode Timing Chart Event Counter Mode Timing Chart 21 HT82A836R March 20, 2008 ...
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... Note that setting the timer enable bit high to turn the timer on, should only be executed after the timer mode 22 HT82A836R /4 is SYS /4 SYS ...
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... This example program sets the Timer/Event Counter the timer mode, which uses the internal system clock as the clock source. timer0 counts from this value to FFFFH note mode bits must be previously setup 23 HT82A836R March 20, 2008 ...
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... PFDD register will be inhibited. When the PFD is disabled note that the PFDD register will be automati- cally cleared. The PFDD contents, the PFD must be en- abled. When the generator is disabled, the PFDD is cleared by hardware. PFD Block Diagram PFDC Register 24 HT82A836R March 20, 2008 ...
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... In cases where both USB and Play interrupts are en- abled and where an USB and Play interrupt occurs si- multaneously, the USB interrupt will always have priority and will therefore be serviced first. Suitable masking of the individual interrupts using the interrupt registers can prevent simultaneous occurrences. 25 HT82A836R Priority Vector 1 04H 2 08H 3 ...
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... Rev. 1.00 INTC0 Register INTC1 Register 26 HT82A836R March 20, 2008 ...
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... When the HT82A836R receives a USB Sus- pend signal from the host PC, the suspend line, bit0 of the USC register, in the HT82A836R is set and a USB interrupt is also triggered. Also when the device re- ceives a Resume signal from the host PC, the resume line, bit3 of the USC register, is set and a USB interrupt generated ...
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... ADF, which is bit 5 in the MFI1C register, will be set. The interrupt vector for the A/D Interrupt is the Multi-function interrupt located at 014H. Therefore if the Multi-function and A/D Interrupt are enabled, the stack is MFI1C Register 28 HT82A836R March 20, 2008 ...
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... Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory ad- 29 HT82A836R March 20, 2008 ...
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... Pro- gram Counter and the Stack Pointer will be cleared to 0 and the TO flag will be set Refer to the A.C. Characteristics for t details. SST WDT Time-out Reset during Power Down Timing Chart 30 HT82A836R must exist for LVR March 20, 2008 ...
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... HT82A836R USB Reset USB Reset (Normal) (HALT) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 000H 000H uuuu uuuu ...
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... HT82A836R USB Reset USB Reset (Normal) (HALT) 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ...
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... Power Down Mode, the system clock will stop running but the WDT oscillator continues to free-run and to keep the watchdog active. However, to preserve power in certain applications the WDT oscillator can be disabled via a configuration option. 33 HT82A836R USB Reset USB Reset (Normal) (HALT) uuuu uuuu ...
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... If an interrupt request flag is set to 1 be- fore entering the Power Down Mode, the wake-up func- tion of the related interrupt will be disabled. 34 HT82A836R March 20, 2008 ...
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... CLR WDT2 instruction will clear the WDT. Similarly, after the CLR WDT2 instruc- tion has been executed, only a successive CLR WDT1 instruction can clear the Watchdog Timer. Watchdog Timer Register 35 HT82A836R March 20, 2008 ...
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... Five endpoints are included in the USB function of this device. USB Interface The Interface in the HT82A836R device has 5 End- points, known as EP0~EP4. Endpoint 0, EP0, is used for Control transfer. Endpoints EP1 and EP4 are for Inter- rupt transfer, while EP2 supports the Isochronous out transfer ...
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... The AWR register is used to store the current USB de- vice address and also for control of the Remote Wake-up function. The initial value of the AWR register is 00H . The address value extracted from the USB command must not be loaded into this register until the SETUP stage has finished. 37 HT82A836R March 20, 2008 ...
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... USB Endpoint Status Register - USR System Clock Control Register - UCC Rev. 1.00 Device Address Register - AWR 38 HT82A836R March 20, 2008 ...
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... The read only IN bit is used to indicate that the current USB receiving signal from PC host token. NAK This read only bit is used to indicate that the SIE has transmitted a NAK signal to the host in response to the PC host IN or OUT token. Endpoint Stall Register - STALL 39 HT82A836R March 20, 2008 ...
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... The read only READY bit is used to indicate that the desired FIFO is ready. LEN0 The read only LEN0 bit is used to indicate that the host has sent a 0-sized packet to the MCU. This bit must be cleared by a read action to the corresponding FIFO. Miscellaneous Register - MISC 40 HT82A836R March 20, 2008 ...
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... SUSP2 bit, which is bit4 of the UCC register. When the resume signal is sent out by the host, the HT82A836R will be woken up the by the USB interrupt and the RESUME bit, which is bit 3 of the USC register, will be set. In order to make the device operate correctly, the program must set the USBCKEN bit and clear the SUSP2 bit ...
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... Speaker Volume Control Table 42 HT82A836R Result (dB) USVC 101_1100 24 25 101_1011 101_1010 26 101_1001 27 101_1000 28 101_0111 29 101_0110 30 101_0101 31 101_0100 32 March 20, 2008 ...
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... DAC input data register at the falling edge of DAC_WR_TRIG. Otherwise, these two registers are used to define the 16-bit DAC output limit (repeated below). Rev. 1.00 Function DAC output limit low byte DAC output limit high byte 43 HT82A836R /2, which DD March 20, 2008 ...
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... DAC data high byte=80H ;Write 8000H to DAC set [02FH].3 clr [02FH].3 ;----------------------------------------------------------- mov a,FIFO_TEMP ;Restore WDTS value mov WDTS,a ;Quit DAC Write Data mode ;----------------------------------------------------------- Rev. 1.00 RECORD_IN_L RECORD_IN_H PCM (Low byte) PCM (High byte) N/A 44 HT82A836R Law March 20, 2008 ...
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... The PGA function is controlled using the PGA_CTRL register within which there is six bits to control the gain value. This gain value ranges from 0dB maxi- mum of 19.5dB, in steps of 0.5dB, and is selected using the PGA0~PGA5 bits. PGA Block Diagram 45 HT82A836R March 20, 2008 ...
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... To Disable the SPI bus SCK, SDI, SDO, SCS floating. SPI Operation All communication is carried out using the 4-line inter- face for both Master or Slave Mode. The timing diagram shows the basic operation of the bus. SPI Block Diagram 46 HT82A836R March 20, 2008 ...
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... SPI function pin the Master Mode the SCK line will be either high or low depending upon the clock po- larity configuration option the Slave Mode the SCK line will floating condition. If SBEN is low then the bus will be disabled. 47 HT82A836R March 20, 2008 ...
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... WCOL bit can be disabled or enabled by a SIO_WCOL bit of MODE_CTRL register. Programming Considerations When the device is placed into the Power Down Mode note that data reception and transmission will continue. The TRF bit is used to generate an interrupt when the data has been transferred or received. 48 HT82A836R March 20, 2008 ...
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... Chip Select Function Enable ;falling edge change data SIO ; SIO SYS ;clear TRF flag ;clear Interrupt SPI flag ;MSB shift first ;Chip Select Enable ;SPI Enable, SCS will go low ;SPI Interrupt Disable ;SPI Interrupt Enable ;set at SPI Interrupt 49 HT82A836R March 20, 2008 ...
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... R_D5 R_D4 R_D3 R_D2 R_D13 R_D12 R_D11 R_D10 PLAY_DATAL_H PLAY_DATAR_L PCM (Left Channel PCM (Right Channel High Byte) Low Byte) N/A Law (Left Channel) 50 HT82A836R PL_D1 PL_D0 PL_D9 PL_D8 PR_D1 PR_D0 PR_D9 PR_D8 R_D1 R_D0 R_D9 R_D8 PLAY_DATAR_H PCM (Right Channel ...
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... PWM operation impor- /128, while tant to note how the single PWM cycle is subdivided into SYS 4 individual modulation cycles, numbered from 0~3 and how the AC value is related to the PWM value. 51 HT82A836R PWM Cycle PWM Cycle Frequency Duty f /256 ...
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... The following diagram illustrates the waveforms associ- ated with the 7+1 mode of PWM operation impor- tant to note how the single PWM cycle is subdivided into 2 individual modulation cycles, numbered from 0~1 and how the AC value is related to the PWM value in the 7+1 PWM Mode. 52 HT82A836R DC (Duty Cycle) DC+1 128 DC 128 ...
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... PWM output configuration options must first be selected. mov a,64h ; setup PWM0 value of 100 decimal which is 64H mov PWM0,a clr PWMC.PWM_MOD0 ; setup pin PWM0 to the 6+2 PWM Mode set PWMC.PWM_EN0 ; enable PWM0 output : : clr PWMC.PWM_EN0 ; disable PWM0 output Rev. 1.00 PWM Control Register - PWMC 53 HT82A836R March 20, 2008 ...
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... A/D converter, together with its associated registers. A/D Converter Data Registers - ADRL, ADRH For the HT82A836R device, which has a 12-bit A/D con- verter, two registers are required, a high byte register, known as ADRH, and a low byte register, known as ADRL, to store the 12-bit analog to digital conversion value ...
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... The AVDD4 power supply pin is used as the A/D converter reference voltage, and as such analog inputs must not be allowed to exceed this value. Appropriate measures should also be taken to ensure that the AVDD4 pin remains as stable and noise free as possible. ADCR Register 55 HT82A836R March 20, 2008 ...
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... A/D converter. After an A/D conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can con- tinue with other functions. A/D Conversion Timing 56 HT82A836R March 20, 2008 ...
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... A/D channel selection bits change value the A/D converter must be re-initialised. This is achieved by pulsing the START bit in the ADCR register immediately after the channel selection bits have changed state. Example: using an EOCB polling method to detect the end of conversion for the HT82A836R. clr EADI mov a,00000001 B mov ACSR,a ...
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... Example: using an interrupt method to detect the end of conversion for the HT82A836R. clr EADI ; disable ADC interrupt mov a,00000001B mov ACSR,a mov a,00100000B mov ADCR Start_conversion: clr ADF set EMF1I set EADI set EMI clr START set START clr START : : : ; ADC interrupt service routine ...
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... A/D Transfer Function As the HT82A836R device contains a 12-bit A/D converter, their full-scale converted digitised value is equal to FFFH. Since the full-scale analog input value is equal to the voltage, this gives a single bit analog input value of V following graphs show the ideal transfer function between the analog input value and the digitised output value for the A/D converters ...
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... PF0~PF3: wake-up enable or disable (bit option) 13 PA0~PA7: CMOS or NMOS output type (bit option) Watchdog Options 14 WDT: enable or disable 15 CLRWDT instructions: one or two instructions 16 WDT Clock Source WDT oscillator SYS LVR Options 17 LVR function: enable or disable TBHP Options 18 TBHP enable or disable Rev. 1.00 Options 60 HT82A836R March 20, 2008 ...
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... Application Circuits Rev. 1.00 61 HT82A836R March 20, 2008 ...
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... These instructions are the key to decision making and branching within the pro- gram perhaps determined by the condition of certain in- put switches or by the condition of internal data bits. 62 HT82A836R March 20, 2008 ...
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... Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Description 63 HT82A836R Cycles Flag Affected AC, OV Note AC AC ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 Description 64 HT82A836R Cycles Flag Affected 1 None Note 1 ...
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... Operation ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev. 1.00 65 HT82A836R March 20, 2008 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev. 1.00 addr 66 HT82A836R March 20, 2008 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev. 1. HT82A836R March 20, 2008 ...
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... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev. 1.00 addr 68 HT82A836R March 20, 2008 ...
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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev. 1.00 Stack Stack Stack [m]. 0~6) 69 HT82A836R March 20, 2008 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev. 1.00 [m]. 0~6) 70 HT82A836R March 20, 2008 ...
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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev. 1.00 [ HT82A836R March 20, 2008 ...
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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev. 1.00 0 [m] [ HT82A836R March 20, 2008 ...
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... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev. 1.00 [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 73 HT82A836R March 20, 2008 ...
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... The result is stored in the Data Memory. Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev. 1.00 74 HT82A836R March 20, 2008 ...
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... Package Information 80-pin LQFP (10´10) Outline Dimensions Symbol Rev. 1.00 Dimensions in mm Min. Nom. 11.9 9.9 11.9 9.9 0.4 0.16 1.35 0.1 0.45 0 HT82A836R Max. 12.1 10.1 12.1 10.1 1.45 1.6 0.75 0.2 7 March 20, 2008 ...
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... QFP (14´20) Outline Dimensions Symbol Rev. 1.00 Dimensions in mm Min. Nom. 18.5 13.9 24.5 19.9 0.65 0.3 2.5 0 HT82A836R Max. 19.2 14.1 25.2 20.1 3.1 3.4 1.4 0.2 7 March 20, 2008 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 77 HT82A836R March 20, 2008 ...